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preliminary technical data sharc and the sharc logo are registered trademarks of ana log devices, inc. sharc processors adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469 /adsp-21469w rev. pre information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.3113 ? 2009 analog devices, inc. all rights reserved. summary note: this datasheet is preliminary. this document contains material that is subject to change without notice. high performance 32-bit/40-bit floating point processor optimized for high performance audio processing single-instruction, multiple-data (simd) computational architecture on-chip memory5 mbits of on-chip ram, 4 mbits of on-chip rom up to 450 mhz operating frequency automotive applicationssever al models are available for automotive products with special manufacturing. see automotive products on page 68 code compatible with all other members of the sharc family the adsp-2146x processors are available with unique audio- centric peripherals such as the digital applications interface, dtcp (digital transmission content protection protocol), serial ports, precision clock generators, s/pdif transceiver, asynchronous samp le rate converters, input data port, and more. for complete ordering information, see automotive prod- ucts on page 68 and ordering guide on page 68 . figure 1. function al block diagram internal memory i/f block 0 ram/rom b0d 64-bit instruction cache 5 stage sequencer pex pey pmd 64-bit iod0 32-bit epd bus 64-bit core bus cross bar dai routing/pins s/pdif tx/rx pcg a - d dpi routing/pins spi/b uart block 1 ram/rom block 2 ram block 3 ram ami ddr2 ctl ep external port pin mux timer 1 - 0 sport 7 - 0 asrc 3 - 0 pwm 3 - 0 dag1/2 timer idp/ pdap 7 - 0 twi iod0 bus dtcp/ mtm pcg c - d core flags jtag dmd 64-bit pmd 64-bit dmd 64-bit core flags iod1 32-bit peripheral bus b1d 64-bit b2d 64-bit b3d 64-bit dpi peripherals dai per ipherals pe ripherals external port s thermal diode fft fir iir link port 1 - 0 mlb spep bus internal memory simd core peripheral bus 32-bit flagx/irqx/ tmrexp
rev. pre | page 2 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data table of contents summary ............................................................... 1 general description ................................................. 3 family core architecture ........................................ 4 family peripheral architecture ................................ 7 system design .................................................... 11 development tools ............................................. 12 additional information ........................................ 13 pin function descriptions ....................................... 14 specifications ........................................................ 19 operating conditions .......................................... 19 electrical characteristics ....................................... 20 package information ........................................... 21 esd sensitivity ................................................... 21 power dissipation ............................................... 21 absolute maximum ratings .................................. 21 timing specifications .......................................... 21 output drive currents ......................................... 58 test conditions .................................................. 58 capacitive loading .............................................. 58 thermal characteristics ....................................... 59 csp_bga ball assignment C adsp-21462w/adsp- 21465w/adsp-21469w .. ..................................... 60 csp_bga ball assignment - adsp-21467/adsp-21469 . 63 outline dimensions ............................................... 66 automotive products .............................................. 67 ordering guide ..................................................... 67
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 3 of 68 | november 2009 general description the adsp-21462w/adsp-21465w/adsp-21467/ adsp-21469/adsp-21469w sharc ? processors are members of the simd sharc family of dsps that feature analog devices' super harvard architectu re. the processors are source code compatible with the adsp-2126x, adsp-2136x, adsp- 2137x, and adsp-2116x dsps as we ll as with first generation adsp-2106x sharc processors in sisd (single-instruction, single-data) mode. these new pr ocessors are 32- bit/40-bit float- ing point processors optimize d for high performance audio applications with its large on-chip sram, multiple internal buses to eliminate i/o bottlenec ks, and an innovative digital applications interface (dai). table 1 shows performance benchmarks for the adsp-2146x processors. table 2 shows the features of the individual product offerings. the diagram on page 1 shows the two clock domains that make up the adsp-2146x processors. th e core clock domain contains the following features. ? two processing elements (p ex, pey), each of which com- prises an alu, multiplier, shifter, and data register file ? data address generators (dag1, dag2) ? program sequencer wi th instruction cache ? one periodic interval timer with pinout table 1. processor benchmarks benchmark algorithm speed (at 450 mhz) 1024 point complex fft (radix 4, with reversal) 20.44 s fir filter (per tap) 1 1 assumes two files in multichannel simd mode 1.11 ns iir filter (per biquad) 1 4.43 ns matrix multiply (pipelined) [3 3] [3 1] [4 4] [4 1] 10.0 ns 17.78 ns divide (y/) 6.67 ns inverse square root 10.0 ns table 2. sharc family features 1 feature adsp-21462w adsp-21465w adsp-21467 adsp-21469 adsp-21469w frequency 400 mhz 400 mhz 450 mhz 450 mhz 400 mhz ram 5m bits rom n/a 4m bits 4m bits n/a n/a audio decoders in rom 2 no yes yes no no pulse-width modulation yes s/pdif yes dtcp 3 yes yes no no no ddr2 memory interface yes ddr2 memory bus width 16 bits direct dma from sports to external memory yes fir, iir, fft accelerator yes mlb interface yes yes no no yes idp yes serial ports 8 dai (sru)/dpi (sru2) 20/14 pins uart 1 link ports 2 s/pdif transceiver 1 ami interface with 8-bit support yes spi 2 twi yes src performance C128 db package 324-ball csp_bga 1 w = automotive grade product. see automotive products on page 68 for more information. 2 audio decoding algorithms include pcm, dolby digital ex, dolby prologic iix, dts 96/24, neo:6, dts es, mpeg-2 aac, mp3, and functions like bass management, delay, speake r equalization, graphic equalization, and more. decoder/post-processor algorithm combin ation support varies depending upon the chip version and the system configurati ons. please visit www.analog.com for complete information. 3 the adsp-21462w and adsp-21465w proc essors provide the digital trans- mission content protection protocol, a pr oprietary security protocol. contact your analog devices sales of fice for more information. table 2. sharc family features 1 (continued) feature adsp-21462w adsp-21465w adsp-21467 adsp-21469 adsp-21469w
rev. pre | page 4 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data ? pm and dm buses capable of supporting 2x64-bit data transfers between me mory and the core at every core pro- cessor cycle ?on-chip sram (5m bit) ? on-chip mask-programmable rom (4m bit) ? jtag test access port for em ulation and boundary scan. the jtag provides software debug through user break- points which allows flexible exception handling. the block diagram of the adsp-2146x on page 1 also shows the peripheral clock domain (also known as the i/o processor) and contains the following features: ?iod0 (peripheral dma) and iod1 (external port dma) buses for 32-bit data transfers ? peripheral and external port buses for core connection ?external port with an ami and ddr2 controller ?4 units for pwm control ? 1 mtm unit for internal-to- internal memory transfers ? digital applications interface that includes four precision clock generators (pcg), a input data port (idp) for serial and parallel interconnect, an s/pdif receiver/transmitter, four asynchronous sample rate converters, eight serial ports, a flexible signal routing unit (dai sru). ? digital peripheral interface that includes two timers, a 2- wire interface, two uarts, two serial peripheral interfaces (spi), 2 precision clock generators (pcg) and a flexible sig- nal routing unit (dpi sru). as shown in the functional block diagram on page 1 , the processor uses two computational units to deliver a significant performance increase over the pr evious sharc processors on a range of dsp algorithms. fabricated in a state-of-the-art, high speed, cmos process, the processor achieves an instruction cycle time of 2.22 ns at 450 mh z and 2.5 ns at 400 mhz. with its simd computational hardware , the processors can perform 2.7 gflops running at 450 mhz and 2.4 gflops running at 400 mhz. family core architecture the adsp-2146x is code compatible at the assembly level with the adsp-2137x, adsp-2136x, adsp-2126x, adsp-21160, and adsp-21161, and with the fi rst generation adsp-2106x sharc processors. the adsp-2146x shares architectural fea- tures with the adsp-2126x, adsp-2136x, adsp-2137x, and adsp-2116x simd sharc processors, as shown in figure 2 and detailed in the following sections. simd computational engine the adsp-2146x contai ns two computational processing ele- ments that operate as a single-instruction, multiple-data (simd) engine. the processing el ements are referred to as pex and pey and each contains an alu, multiplier, shifter, and reg- ister file. pex is always active, and pey may be enabled by setting the peyen mode bit in the mode1 register. when this mode is enabled, the same instru ction is executed in both pro- cessing elements, but each proc essing element operates on different data. this architecture is efficient at executing math intensive dsp algorithms. entering simd mode also has an effect on the way data is trans- ferred between memory and the processing elements. when in simd mode, twice the data bandwidth is required to sustain computational operation in the pr ocessing elements. because of this requirement, entering simd mode also doubles the band- width between memory and the processing elements. when using the dags to transfer data in simd mode, two data values are transferred with each access of memory or the register file. independent, parallel computation units within each processing element is a set of computational units. the computational units consist of an arithmetic/logic unit (alu), multiplier, and shifter. these units perform all opera- tions in a single cycl e. the three units within each processing element are arranged in paralle l, maximizing computational throughput. single multifunctio n instructions execute parallel alu and multiplier operations . in simd mode, the parallel alu and multiplier operations occur in both processing ele- ments. these computation unit s support ieee 32-bit single- precision floating-point, 40-bit extended precision floating- point, and 32-bit fixed-point data formats. timer a core timer that can generate pe riodic software interrupts. the core timer can be configured to use flag3 as a timer expired signal. data register file a general-purpose data register file is contained in each pro- cessing element. the register fi les transfer data between the computation units and the data buses, and store intermediate results. these 10-port, 32-regist er (16 primary, 16 secondary) register files, combined with the processors enhanced harvard architecture, allow unconstrained data flow between computa- tion units and internal memory. the registers in pex are referred to as r0-r15 and in pey as s0-s15. context switch many of the processors register s have secondary registers that can be activated during interrupt servicing for a fast context switch. the data registers in the register file, the dag registers, and the multiplier result register s all have secondary registers. the primary registers are active at reset, while the secondary registers are activated by control bits in a mode control register. universal registers these registers can be used fo r general-purpose tasks. the ustat (4) registers allow easy bit manipulations (set, clear, toggle, test, xor) for all system registers (control/status) of the core. the data bus exchange register (px) permits data to be passed between the 64-bit pm data bus and the 64-bit dm data bus, or between the 40-bit register file and the pm data bus. these reg- isters contain hardware to hand le the data width difference.
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 5 of 68 | november 2009 single-cycle fetch of instruction and four operands the adsp-2146x features an enha nced harvard architecture in which the data memory (dm) bu s transfers data and the pro- gram memory (pm) bus transfer s both instructions and data (see figure 2 ). with the its separate program and data memory buses and on-chip instruction ca che, the processor can simulta- neously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. instruction cache the adsp-2146x includes an on -chip instruction cache that enables three-bus operat ion for fetching an instruction and four data values. the cache is select iveonly the instructions whose fetches conflict with pm bus data accesses are cached. this cache allows full speed executio n of core, looped operations such as digital filter multiply -accumulates, and fft butterfly processing. data address generators wi th zero-overhead hardware circular buffer support the adsp-2146xs two data addr ess generators (dags) are used for indirect addressing and implementing circular data buffers in hardware. circular buffers allow efficient program- ming of delay lines and other data structures required in digital signal processing, and are common ly used in digi tal filters and fourier transforms. the two dags of the processors contain sufficient registers to allow the creation of up to 32 circular buff- ers (16 primary register sets , 16 secondary). the dags automatically handle address pointer wraparound, reduce over- head, increase performance, and simplify implementation. circular buffers can start and end at any memory location. flexible instruction set the 48-bit instruction word acco mmodates a variety of parallel operations, for concise prog ramming. for example, the adsp-2146x can conditio nally execute a multip ly, an add, and a figure 2. sharc co re block diagram s s s s ss ss s s s s s ss s s ss s s s ss
rev. pre | page 6 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data subtract in both processing el ements while branching and fetch- ing up to four 32-bit values from memoryall in a single instruction. variable instruction set architecture (visa) in addition to supporting the st andard 48-bit instructions from previous sharc processors, the adsp-2146x supports new instructions of 16 and 32 bits. this feature, called variable instruction set architecture (visa), drops redundant/unused bits within the 48-bit instruction to create more efficient and compact code. the program sequ encer supports fetching these 16-bit and 32-bit instructions from both internal and external ddr2 memory. source modules need to be built using the visa option, in order to allow co de generation tools to create these more efficient opcodes. on-chip memory the processors contain 5 mbits of internal ram. each block can be configured for different combinations of code and data storage (see table 4 ). each memory block supports single-cycle, independent accesses by the core processor and i/o processor. the adsp-2146x memory architectu re, in combination with its separate on-chip buses, allow tw o data transfers from the core and one from the i/o processor, in a single cycle. the processors sram can be configured as a maximum of 160k words of 32-bit data, 320k words of 16-bit data, 106.7k words of 48-bit instructions (or 40 -bit data), or combinations of different word sizes up to 5 megabit. all of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. a 16-bit float- ing-point storage format is suppo rted that effectively doubles the amount of data that may be stored on-chip. conversion between the 32-bit floating-point and 16-bit floating-point for- mats is performed in a single instruction. while each memory block can store combinations of code and data, accesses are most efficient when one block st ores data using the dm bus for transfers, and the other block stor es instructions and data using the pm bus for transfers. using the dm bus and pm buses, with one bus dedicated to a memory block, assures single-c ycle execution with two data transfers. in this ca se, the instruction must be available in the cache. the memory map in table 3 displays the internal memory address space of the adsp-21462w, adsp-21469 and adsp-21469w processors. the memory map in table 4 displays the internal memory address space of the adsp-21465w and adsp-21467 processors. the 48-bit space section describes what this address range looks like to an instruction that retrieves 48-bit memory. the 32-bit section describes what this ad dress range looks like to an instruction that retrieves 32-bit memory. on-chip memory bandwidth the internal memory architecture allows programs to have four accesses at the same time to any of the four blocks (assuming there are no block conflicts). th e total bandwidth is realized using the dmd and pmd buses (2 x 64-bits, cclk speed) and the iod0/1 buses (2 x 32-bit, pclk speed). table 3. adsp-21462w/adsp-21469/adsp- 21469w internal memory space iop registers 0x0000 0000C0x0003 ffff long word (64 bits) extended precision normal or instruction word (48 bits) normal word (32 bits) short word (16 bits) block 0 ram 0x0004 9000C0x0004 efff block 0 ram 0x0008 c000-0x0009 3fff block 0 ram 0x0009 2000-0x0009 dfff block 0 ram 0x0012 4000C0x0013 bfff reserved 0x0004 f000C0x0005 8fff reserved 0x0009 4000C0x0009 5554 reserved 0x0009 e000C0x000b 1fff reserved 0x0013 c000C0x0016 3fff block 1 ram 0x0005 9000C0x0005 efff block 1 ram 0x000a c000-0x000b 3fff block 1 ram 0x000b 2000-0x000b dfff block 1 ram 0x0016 4000-0x0017 bfff reserved 0x0005 f000C0x0005 ffff reserved 0x000b 4000C0x000b 5554 reserved 0x000b e000C0x000b ffff reserved 0x0017 c000C0x0017 ffff block 2 ram 0x0006 0000C0x0006 3fff block 2 ram 0x000c 0000C0x000c 5554 block 2 ram 0x000c 0000-0x000c 7fff block 2 ram 0x0018 0000C0x0018 ffff reserved 0x0006 4000C0x0006 ffff reserved 0x000c 5555C0x000d 5554 reserved 0x000c 8000C0x000d ffff reserved 0x0019 0000C0x001b ffff block 3 ram 0x0007 0000C0x0007 3fff block 3 ram 0x000e 0000C0x000e 5554 block 3 ram 0x000e 0000C0x000e 7fff block 3 ram 0x001c 0000C0x001c ffff reserved 0x0007 4000C0x0007 ffff reserved 0x000e 5555C0x000f 5554 reserved 0x000e 8000C0x000f ffff reserved 0x001d 0000C0x001f ffff
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 7 of 68 | november 2009 rom based security the adsp-2146x has a rom securi ty feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code when enabled. when using this feature, the pr ocessor does not boot-load any external code, executing exclusively from internal rom. addi- tionally, the processor is not freely accessible via the jtag port. instead, a unique 64-bit key, wh ich must be scanned in through the jtag or test access port will be assigned to each customer. the device ignores a wrong key. emulation features and exter- nal boot modes are on ly available after the correct key is scanned. digital transmission content protection the dtcp specification defines a cryptographic protocol for protecting audio entertainment content from illegal copying, intercepting, and tampering as it traverses high performance digital buses, such as the ieee 1394 standard . only legitimate entertainment content delivered to a source device via another approved copy protection syst em (such as the dvd content scrambling system) is protected by this copy protection system. this feature is availabl e on the adsp-21462w and adsp-21465w processors only. licensing through dtla is required for these products. visit www.dtcp.com for more information. family peripheral architecture the adsp-2146x family contains a rich set of peripherals that support a wide variety of applications including high quality audio, medical imaging, communications, military, test equip- ment, 3d graphics, speech recognit ion, motor control, imaging, and other applications. external port the external port interface supports access to the external mem- ory through core and dma accesses. the external memory address space is divided into four banks. any bank can be pro- grammed as either asynchronous or synchronous memory. the external ports are comprised of the following modules. ? an asynchronous memory interface which communicates with sram, flash, and other devices that meet the stan- dard asynchronous sram access protocol. the ami table 4. adsp-21465w/adsp-21467 internal memory space iop registers 0x0000 0000C0x0003 ffff long word (64 bits) extended precision normal or instruction word (48 bits) normal word (32 bits) short word (16 bits) block 0 rom 0x0004 0000C0x0004 7fff block 0 rom 0x0008 0000C0x0008 aaa9 block 0 rom 0x0008 0000C0x0008 ffff block 0 rom 0x0010 0000C0x0011 ffff reserved 0x0004 8000C0x0004 8fff reserved 0x0008 aaaaC0x0008 bfff reserved 0x0009 0000C0x0009 1fff reserved 0x0012 0000C0x0012 3fff block 0 ram 0x0004 9000C0x0004 efff block 0 ram 0x0008 c000-0x0009 3fff block 0 ram 0x0009 2000-0x0009 dfff block 0 ram 0x0012 4000C0x0013 bfff reserved 0x0004 f000C0x0004 ffff reserved 0x0009 4000C0x0009 5554 reserved 0x0009 e000C0x0009 ffff reserved 0x0013 c000C0x0013 ffff block 1 rom 0x0005 0000C0x0005 7fff block 1 rom 0x000a 0000C0x000a aaa9 block 1 rom 0x000a 0000C0x000a ffff block 1 rom 0x0014 0000-0x0015 ffff reserved 0x0005 8000C0x0005 8fff reserved 0x000a aaaaC0x000a bfff reserved 0x000b 0000C0x000b 1fff reserved 0x0016 0000-0x0016 3fff block 1 ram 0x0005 9000C0x0005 efff block 1 ram 0x000a c000-0x000b 3fff block 1 ram 0x000b 2000-0x000b dfff block 1 ram 0x0016 4000-0x0017 bfff reserved 0x0005 f000C0x0005 ffff reserved 0x000b 4000C0x000b 5554 reserved 0x000b e000C0x000b ffff reserved 0x0017 c000C0x0017 ffff block 2 ram 0x0006 0000C0x0006 3fff block 2 ram 0x000c 0000C0x000c 5554 block 2 ram 0x000c 0000-0x000c 7fff block 2 ram 0x0018 0000C0x0018 ffff reserved 0x0006 4000C0x0006 ffff reserved 0x000c 5555C0x000d 5554 reserved 0x000c 8000C0x000d ffff reserved 0x0019 0000C0x001b ffff block 3 ram 0x0007 0000C0x0007 3fff block 3 ram 0x000e 0000C0x000e 5554 block 3 ram 0x000e 0000C0x000e 7fff block 3 ram 0x001c 0000C0x001c ffff reserved 0x0007 4000C0x0007 ffff reserved 0x000e 5555C0x0000f 5554 reserved 0x000e 8000C0x000f ffff reserved 0x001d 0000C0x001f ffff
rev. pre | page 8 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data supports 14m words of extern al memory in bank 0 and 16m words of external memory in bank 1, bank 2, and bank 3. ? a ddr2 dram controller. external memory devices up to 2 gbits in size can be supported. ? arbitration logic to coordinate core and dma transfers between internal and external memory over the external port. external memory the external port on the adsp -2146x sharc provides a high performance, glueless interface to a wide variety of industry- standard memory devices. the ex ternal port may be used to interface to synchronous and/or asynchronous memory devices through the use of its separate internal ddr2 memory control- ler. the 16-bit ddr2 dram controller connects to industry- standard synchronous dram devi ces, while the second 8-bit asynchronous memory controller is intended to interface to a variety of memory devices. four memory select pins enable up to four separate devices to co exist, supporting any desired com- bination of synchronous and asynchronous device types. non ddr2 dram external memory address space is shown in table 5 . simd access to external memory the ddr2 controller on the adsp-2146x processor supports simd access on the 64-bit epd (e xternal port da ta bus) which allows to access the complementar y registers on the pey unit in the normal word space (nw). th is improves performance since there is no need to explicitly lo ad the complimentary registers as in sisd mode. visa and non visa access to external memory the ddr2 controller on the adsp-2146x processor supports visa code operation which reduces the memory load since the visa instructions are compressed. moreover, bus fetching is reduced because in the best ca se one 48-bit fetch contains 3 valid instructions. code execution from the traditional non- visa operation is also supported . note that code execution is only supported from bank 0 regardless of visa/non-visa. ddr2 support the adsp-2146x supports a 16-bit ddr2 interface operating at a maximum frequency of half the core clock. execution from external memory is supported. ex ternal memory devices up to 2 gbits in size can be supported. ddr2 dram controller the ddr2 dram controller provides an 16-bit interface to up to four separate banks of industry-standard ddr2 dram devices. fully compliant with the ddr2 dram standard, each bank can has its own memory select line (ddr2_cs3 C ddr2_cs0), and can be configured to contain between 32m bytes and 256m bytes of memory . ddr2 dram external mem- ory address space is shown in table 6 a set of programmable timing parameters is available to config- ure the ddr2 dram banks to support memory devices. note that the external memory bank addresses shown are for normal-word (32-bit) accesses. if 48-bit instructions as well as 32-bit data are both placed in the same external memory bank, care must be taken while mappin g them to avoid overlap. in case of 16-bit wide external me mory, two 48-bit instructions are stored in six 32-bit wide memory locations. for example, if 2k instructions are placed in 16-bit wide external memory starting at the bank 0 normal-word base address 0x0030 0000 (corre- sponding to instruction addr ess 0x0020 0000) and ending at address 0x0030 0bff (corresponding to instruction address 0x0020 07ff), then data buffers ca n be placed starting at an address that is offset by 3k 32-bi t words (for example, starting at 0x0030 0c00). asynchronous memory controller the asynchronous memory controller provides a configurable interface for up to four sepa rate banks of memory or i/o devices. each bank can be independently programmed with dif- ferent timing parameters, enabling connection to a wide variety of memory devices including sram, flash, and eprom, as well as i/o devices that interface with standard memory control lines. bank 0 occupies a 14m word window and banks 1, 2, and 3 occupy a 16m word window in the processors address space but, if not fully populated, th ese windows are not made contigu- ous by the memory controller logic. external port throughput the throughput for the extern al port, based on a 400 mhz clock, is 66 m bytes/s for the ami and 800 m bytes/s for ddr2. link ports two 8-bit wide link ports can connect to the link ports of other dsps or peripherals. link ports are bidirectional ports having eight data lines, an acknowledge line and a clock line. link ports can operate at a maximu m frequency of 166 mhz. table 5. external memory for non ddr2 dram addresses bank size in words address range bank 0 14m 0x0020 0000 C 0x00ff ffff bank 1 16m 0x0400 0000 C 0x04ff ffff bank 2 16m 0x0800 0000 C 0x08ff ffff bank 3 16m 0x0c00 0000 C 0x0cff ffff table 6. external memory for ddr2 dram addresses bank size in words address range bank 0 62m 0x0020 0000 C 0x03ff ffff bank 1 64m 0x0400 0000 C 0x07ff ffff bank 2 64m 0x0800 0000 C 0x0bff ffff bank 3 64m 0x0c00 0000 C 0x0fff ffff
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 9 of 68 | november 2009 medialb the adsp-21462w, adsp-21465w and adsp-21469w have a mlb interface which allows the processor to function as a media local bus device. it includes support for both 3-pin as well as 5-pin media local bus protocol s. it supports speeds up to 1024 fs (49.25 mbits/sec, fs = 48.1 khz) and up to 31 logical chan- nels, with up to 124 bytes of data per media local bus frame. the mlb interface on adsp -2146x supports most25 and most50 data rates. the isochronous mode of transfer is not supported in adsp-2146x processor. pulse-width modulation the pwm module is a flexible , programmable, pwm waveform generator that can be programmed to generate the required switching patterns for various a pplications related to motor and engine control or audio power control. the pwm generator can generate either center-aligned or edge-align ed pwm wave- forms. in addition, it can gene rate complementary signals on two outputs in paired mode or independent signals in non- paired mode (applicable to a single group of four pwm waveforms). the entire pwm module has four groups of four pwm outputs each. therefore, this module generates 16 pwm outputs in total. each pwm group produces two pairs of pwm signals on the four pwm outputs. the pwm generator is capable of operating in two distinct modes while generating center-aligned pwm waveforms: single update mode or double update mode. in single update mode the duty cycle values are programmab le only once per pwm period. this results in pwm patterns that are symmetrical about the mid-point of the pwm period. in double update mode, a second updating of the pwm re gisters is implemented at the mid-point of the pwm period. in this mode, it is possible to produce asymmetrical pwm patte rns that produce lower har- monic distortion in three-phase pwm inverters. digital applications interface (dai) the digital applications interface (dai) provides the ability to connect various peripherals to any of the dai pins (dai_p20C1). programs make these connections using the signal routing unit (sru), shown in figure 1 . the sru is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the dai to be intercon- nected under software control. th is allows easy use of the dai associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with noncon- figurable signal paths. the dai also includes eight serial ports, four precision clock generators (pcg), s/pdif tran sceiver, four asrcs, and an input data port (idp). the idp provides an additional input path to the sharc core, configur able as either eight channels of serial data, or a single 20-bi t wide synchronous parallel data acquisition port. each data channel has its own dma channel that is independent from th e processors serial ports. serial ports the adsp-2146x features eight sy nchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as analog devices ad183x family of audio codecs , adcs, and dacs. the serial ports are made up of two data lines, a clock, and frame sync. the data lines can be programmed to either transmit or receive and each data line has a dedicated dma channel. serial ports can support up to 16 transmit or 16 receive channels of audio data when all eight sp orts are enabled, or four full duplex tdm streams of 128 channels per frame. the serial ports operate at a maximum data rate of f pclk /4. serial port data can be automatically transferred to and from on-chip memory/external memory via dedicated dma chan- nels. each of the serial ports can work in conjunction with another serial port to provid e tdm support. one sport pro- vides two transmit signals whil e the other sport provides the two receive signals. the fram e sync and clock are shared. serial ports operate in five modes: ? standard dsp serial mode ?multichannel (tdm) mode ?i 2 s mode ?packed i 2 s mode ? left-justified mode left-justified mode is a mode where in each frame sync cycle two samples of data are transmitted/receivedone sample on the high segment of the frame sync, the other on the low seg- ment of the frame sync. programs have control over various attributes of this mode. each of the serial ports suppo rts the left-justified and i 2 s proto- cols (i 2 s is an industry-standard interface commonly used by audio codecs, adcs, and dacs such as the analog devices ad183x family), with two data pi ns, allowing four left-justified or i 2 s channels (using two stereo de vices) per serial port, with a maximum of up to 32 i 2 s channels. the serial ports permit lit- tle-endian or big-endian transm ission formats and word lengths selectable from 3 bits to 32 bits. for the left-justified and i 2 s modes, data-word lengths are selectable between 8 bits and 32 bits. serial ports offer selectable synchronization and transmit modes as well as optional -law or a-law companding selection on a per channel basis. serial port clocks and frame syncs can be internally or exte rnally generated. the serial ports also contain fr ame sync error detection logic where the serial ports detect fram e syncs that arrive early (for example frame syncs that arrive while the transmission/recep- tion of the previous word is occurring). all the serial ports also share one dedicated error interrupt. s/pdif-compatible digital audio receiver/transmitter the s/pdif receiver/transmitter has no separate dma chan- nels. it receives audio data in serial format and converts it into a biphase encoded signal. the serial data input to the receiver/transmitter ca n be formatted as left justified, i 2 s or right justified with word widt hs of 16, 18, 20, or 24 bits.
rev. pre | page 10 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data the serial data, clock, and frame sync inputs to the s/pdif receiver/transmitter are routed th rough the signal routing unit (sru). they can come from a va riety of sources such as the sports, external pins, the precision clock generators (pcgs), and are controlled by the sru control registers. asynchronous sample rate converter the sample rate converter (asrc) contains four asrc blocks and is the same core as that used in the ad1896 192 khz stereo asynchronous sample rate conver ter and provides up to 128 db snr. the asrc block is used to perform synchronous or asyn- chronous sample rate conversi on across indepe ndent stereo channels, without using internal processor resources. the four src blocks can also be config ured to operat e together to convert multichannel audio data without phase mismatches. finally, the asrc can be used to clean up audio data from jit- tery clock sources such as the s/pdif receiver. input data port the idp provides up to eight se rial input channelseach with its own clock, frame sync, and data inputs. the eight channels are automatically multiplexed into a single 32-bit by eight-deep fifo. data is always formatted as a 64-bit frame and divided into two 32-bit words. the serial protocol is designed to receive audio channels in i2s, left-justi fied sample pair , or right-justi- fied mode. one frame sync cycle indicates one 64-bit left/right pair, but data is sent to the fifo as 32-bit words (that is, one- half of a frame at a time). the processor supports 24- and 32-bit i 2 s, 24- and 32-bit left-justifi ed, and 24-, 20-, 18- and 16-bit right-justified formats. precision clock generators the precision clock generators (pcg) consist of four units, each of which generates a pair of signals (clock and frame sync) derived from a clock input signal. the units, a b, c, and d, are identical in functionality and operate independently of each other. the two signals generated by each unit are normally used as a serial bit clock/frame sync pair. digital peripheral interface (dpi) the digital peripheral interfac e provides connections to two serial peripheral interface port s (spi), one universal asynchro- nous receiver-transmitter (uart) , 12 flags, a 2-wire interface (twi), and two gene ral-purpose timers. serial peripheral (compatible) interface the adsp-2146x sharc processors contain two se rial periph- eral interface ports (spis). the spi is an industry-standard synchronous serial li nk, enabling the spi-compatible port to communicate with other spi comp atible devices. the spi con- sists of two data pins, one device select pin, and one clock pin. it is a full-duplex synchronous seri al interface, supporting both master and slave modes. the sp i port can operate in a multi- master environment by interfacing with up to four other spi- compatible devices, either acting as a master or slave device. the spi-compatible peripheral implementation also features pro- grammable baud rate and clock phase and polarities. the spi- compatible port uses open drai n drivers to support a multimas- ter configuration and to avoid data contention. uart port the processors provide a full-du plex universal asynchronous receiver/transmitter (uart) port, which is fully compatible with pc-standard uarts. the ua rt port provides a simpli- fied uart interface to other peripherals or hosts, supporting full-duplex, dma-support ed, asynchronous transfers of serial data. the uart also has mult iprocessor commun ication capa- bility using 9-bit address detection. this allows it to be used in multidrop networks through th e rs-485 data interface stan- dard. the uart port also includes support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. the uart port supports two modes of operation: ? pio (programmed i/o) C the processor sends or receives data by writing or reading i/o-mapped uart registers. the data is double-buffered on both transmit and receive. ? dma (direct memory access) C the dma controller trans- fers both transmit and receive data. this reduces the number and frequency of interrupts required to transfer data to and from memory. the uart has two dedicated dma channels, one for transmit and one for receive. these dma channels have lower defa ult priority than most dma channels because of their re latively low service rates. the uart port's baud rate, seri al data format, error code gen- eration and status, and interrupts are programmable: ? supporting bit rates ranging from (f pclk / 1,048,576) to (f pclk /16) bits per second. ? supporting data formats from 7 to 12 bits per frame. ? both transmit and receive operations can be configured to generate maskable interrupts to the processor. in conjunction with the general-purpose timer functions, auto- baud detection is supported. timers the adsp-2146x has a total of th ree timers: a core timer that can generate periodic software interrupts and two general pur- pose timers that can generate periodic interrupts and be independently set to operat e in one of three modes: ?pulse waveform generation mode ?pulse width co unt/capture mode ? external event watchdog mode the core timer can be configured to use flag3 as a timer expired signal, and each genera l-purpose timer has one bidirec- tional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32- bit pulse width register. a sin- gle control and status register enables or disables both general- purpose timers independently.
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 11 of 68 | november 2009 2-wire interface port (twi) the twi is a bidirectional 2-wire, serial bus used to move 8-bit data while maintaining compliance with the i 2 c bus protocol. the twi master incorporates the following features: ? 7-bit addressing ? simultaneous master and sl ave operation on multiple device systems with support for multi master data arbitration ? digital filtering and timed event processing ? 100 kbps and 400 kbps data rates ? low interrupt rate i/o processor features the adsp-21462w, adsp-21465w and adsp-21469w i/o processors provide 67 channels of dma, while adsp-21467 and adsp-21469 i/o processors provide 36 channels of dma as well as an extensive set of pe ripherals. these include a 20 lead digital applications interface, which controls: dma controller the processors on-chip dma controller allows data transfers without processor intervention . the dma controller operates independently and invisibly to the processor core, allowing dma operations to occur while th e core is simultaneously exe- cuting its program instructio ns. dma transfers can occur between the adsp-2146xs internal memory and its serial ports, the spi-compatible (serial periph eral interface) ports, the idp (input data port), the parallel da ta acquisition port (pdap) or the uart. up to 67 channels of dma are available on the adsp-2146x processors as shown in table 7 . programs can be downloaded to the adsp-2146x using dma transfers. other dma features include interrupt generation upon completion of dma transfers, and dma chaining for automatic linked dma transfers. delay line dma the adsp-2146x proce ssor provides delay line dma function- ality. this allows processor reads and writes to external delay line buffers (and hence to external memory) with limited core interaction. scatter/gather dma the adsp-2146x processor prov ides scatter/gather dma functionality. this allows processor dma reads/writes to/from non-contin- geous memory blocks. iir accelerator the iir (infinite impulse response) accelerator consists of a 1440 word coefficient memory fo r storage of biquad coeffi- cients, a data memory for storin g the intermediate data and one mac unit. a controller manages th e accelerator. the iir accel- erator runs at the peripheral clock frequency. fft accelerator fft accelerator implements radi x-2 complex/real input, com- plex output fft with no core intervention. fir accelerator the fir (finite impulse response ) accelerator consists of a 1024 word coefficient memory, a 1024 wo rd deep delay line for the data, and four mac units. a controller manages the accelerator. the fir accelerator runs at the peripheral clock frequency. system design the following sections provide an introduction to system design options and power supply issues. program booting the internal memory of the adsp-2146x boots at system power-up from an 8-bit eprom vi a the external port, link port, an spi master, or an spi slave. booting is determined by the boot configuration (bootcfg2C0) pins in table 8 . the running reset feature allows a user to perform a reset of the processor core and peripherals, but without resetting the pll and ddr2 dram controller, or performing a boot. the functionality of the resetout pin also acts as the input for initiating a running reset. for more information, see the adsp-2146x sharc proce ssor hardware reference . table 7. dma channels peripheral dma channels adsp-21462w adsp-21465w adsp-21469w adsp-21467 adsp-21469 sports 16 16 pdap 8 8 spi 2 2 uart 2 2 external port 2 2 link port 2 2 accelerators 2 2 memory-to-memory 2 2 mlb 31 0 table 8. boot mode selection bootcfg2C0 booting mode 000 spi slave boot 001 spi master boot 010 ami boot (for 8-bit flash boot) 011 reserved 100 link port 0 boot 101 reserved
rev. pre | page 12 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data power supplies the processors have separate power supply connections for the internal (v dd_int ), external (v dd_ext ), and analog (v dd_a /agnd) power supplies. the internal and analog sup- plies must meet the v dd_int specifications. the external supply must meet the v dd_ext specification. all external supply pins must be connected to the same power supply. note that the an alog supply pin (v dd_a ) powers the processors internal clock generator pll. to produce a stable clock, it is rec- ommended that pcb designs use an external filter circuit for the v dd_a pin. place the filter components as close as possible to the v dd_a /agnd pins. for an example circuit, see figure 3 . (a recommended ferrite chip is the murata blm18ag102sn1d). to reduce noise coupling, the pcb should use a parallel pair of power and ground planes for v dd_int and gnd. use wide traces to connect the bypass ca pacitors to the analog power (v dd_a ) and ground (agnd) pins. note that the v dd_a and agnd pins specified in figure 3 are inputs to the processor and not the analog ground plane on the boardthe agnd pin should connect directly to digital ground (gnd) at the chip target board jtag emulator connector analog devices dsp tools product line of jtag emulators uses the ieee 1149.1 jtag test access port of the adsp-2146x pro- cessors to monitor and control the target board processor during emulation. analog devices dsp tools product line of jtag emulators provides emulat ion at full processor speed, allowing inspection and modifica tion of memory, registers, and processor stacks. the processor' s jtag interface ensures that the emulator will not affect targ et system load ing or timing. for complete information on analog devices sharc dsp tools product line of jtag emulator operation, see the appro- priate emulator hardware user's guide. development tools the adsp-2146x processors are su pported with a complete set of crosscore ? software and hardware development tools, including analog devices emulators and visualdsp++ ? devel- opment environment. the same emulator hardware that supports other sharc processors also fully emulates the adsp-2146x processors. ez-kit lite evaluation board for evaluation of the processors, use the ez-kit lite ? board being developed by analog devices. the board comes with on- chip emulation capabilities and is equipped to enable software development. multiple daug hter cards are available. designing an emulator-compatible dsp board (target) the analog devices family of emulators are tools that every dsp developer needs to test an d debug hardware and software systems. analog devices has supplied an ieee 1149.1 jtag test access port (tap) on each jtag dsp. nonintrusive in- circuit emulation is a ssured by the use of the processors jtag interfacethe emulator does not affect target syst em loading or timing. the emulator uses the tap to access the internal fea- tures of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. the processor must be halted to send data and com- mands, but once an operation has been completed by the emulator, the dsp system is set running at full speed with no impact on system timing. to use these emulators, the target board must include a header that connects the dsps jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor connection s, signal buffering, signal ter- mination, and emulator pod logic, see the ee-68: analog devices jtag emulation technical reference on the analog devices website ( www.analog.com )use site search on ee-68. this document is updated regularly to keep pace with improvements to emulator support. evaluation kit analog devices offers a range of ez-kit lite ? evaluation plat- forms to use as a cost effective method to learn more about developing or prototyping appl ications with analog devices processors, platforms, and softwa re tools. each ez-kit lite includes an evaluation board along with an evaluation suite of the visualdsp++ ? development and debugging environment with the c/c++ compiler, assemble r, and linker. also included are sample applicat ion programs, power supply, and a usb cable. all evaluation versions of the software tools are limited for use only with the ez-kit lite product. the usb controller on the ez-kit lite board connects the board to the usb port of the users pc, enabling the visualdsp++ evaluation suite to emulate the on-board proces- sor in-circuit. this permits the customer to download, execute, and debug programs for the ez-kit lite system. it also allows in-circuit programming of the on -board flash device to store user-specific boot code , enabling the board to run as a standal- one unit without being connected to the pc. with a full version of visualdsp ++ installed (sold separately), engineers can develop software fo r the ez-kit lite or any cus- tom defined system. connecting one of analog devices jtag emulators to the ez-kit lite board enables high speed, non- intrusive emulation. figure 3. analog power (v dd_a ) filter circuit hi ferrite bead chip locate all components close to v dd_a and agnd pins v dd_a 100nf 10nf 1nf adsp-2146x v dd_int agnd
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 13 of 68 | november 2009 additional information this data sheet provides a gene ral overview of the adsp-2146x architecture and functionality. for detailed information on the adsp-2146x family core architecture and instruction set, refer to the adsp-2136x/adsp-2146x sharc processor program- ming reference .
rev. pre | page 14 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data pin function descriptions unused ddr2 pins when the ddr2 controller is not used: ? leave the ddr2 signal pins floating. ? internally, three-state the ddr2 i/o signals. this can be done by setting the dis_ddtcl bit of ddr2ctl0 register. ? power down the receive path by setting the pwd bits of the ddr2padctlx register. ?connect the v dd_ddr2 pins to the v dd_int supply. ?leave v ref floating/unconnected. table 9. pin descriptions name type state during/ after reset description ami_addr 23C0 i/o/t (ipu) high-z/driven low (boot) external address. the processor outputs addresses for external memory and peripherals on these pins. the data pins can be multiplexed to support the pdap (i) and pwm (o). after reset, all ami_addr 23C0 pins are in external memory interface mode and flag(0C3) pins are in flags mode (default). when configured in the idp_pdap_ctl register, idp channel 0 scans the ami_addr 23C0 pins for parallel input data. ami_data 7C0 i/o/t (ipu) high-z external data. the data pins can be multiplexed to support the external memory interface data (i/o), the pdap (i), flags (i/o) and pwm (o). after reset, all ami_data pins are in emif mode and flag(0-3) pins are in flags mode (default). ami_ack i (ipu) memory acknowledge (ami_ack). external devices can deassert ami_ack (low) to add wait states to an external memory access. ami_ack is used by i/o devices, memory controllers, or other peripherals to hold off completion of an external memory access. ami_ms 0C1 o/t (ipu) high-z memory select lines 0C1. these lines are asserted (low) as chip selects for the corre- sponding banks of external memory on the ami interface. the ms 1-0 lines are decoded memory address lines that change at the same time as the other address lines. when no external memory access is occurring the ms 1-0 lines are inactive; they are active however when a conditional memory access instruction is executed, whether or not the condition is true. the ms1 pin can be used in eport/flash boot mode. for more information, see the adsp-2146x sharc proces sor hardware reference. ami_rd o/t (ipu) high-z ami port read enable. ami_rd is asserted whenever the processor reads a word from external memory. ami_wr o/t (ipu) high-z external port write enable. ami_wr is asserted when the processor writes a word to external memory. flag[0]/irq0 i/o (ipu) flag[0] input flag0/interrupt request0. flag[1]/irq1 i/o (ipu) flag[1] input flag1/interrupt request1. flag[2]/irq2 / ami_ms2 i/o (ipu) flag[2] input flag2/interrupt request2/async memory select2. flag[3]/tmrexp/ ami_ms3 i/o (ipu) flag[3] input flag3/timer expired/async memory select3. the following symbols appear in the type column of table 9 : a = asynchronous, i = input, o = output, s = synchronous, a/d = active drive, o/d = open drain, and t = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. the internal pull-up (ipu) and internal pull-down (ipd) resistors ar e designed to hold the internal path from the pins at the e xpected logic levels. to pull-up or pull-down the external pads to the expected logi c levels, use external resistors. internal pull-up/pull-down resi stors cannot be enabled/disabled and the value of these resistors cannot be prog rammed. the range of an ipu resistor can be between 26kC63k . the range of an ipd resistor can be between 31kC85k . in this table, the ddr2 pins are sstl18 co mpliant. all other pins are lvttl compliant.
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 15 of 68 | november 2009 ddr2_addr 15C0 o/t high-z/driven low ddr2 address. ddr2 address pins. ddr2_ba 2-0 o/t high-z/driven low ddr2 bank address input. defines which internal bank an activate, read, write, or precharge co mmand is being applied to. ba 2C0 define which mode registers, including mr, emr, emr(2), and emr(3) are loaded during the load mode register command. ddr2_cas o/t high-z/driven high ddr2 column address strobe. connect to ddr2_cas pin, in conjunction with other ddr2 command pins, defines the operation for the ddr2 to perform. ddr2_cke o/t high-z/driven low ddr2 clock enable output to ddr2. active high signal. connect to ddr2 cke signal. ddr2_cs 3-0 o/t high-z/driven high ddr2 chip select. all commands are masked when ddr2_cs 3-0 is driven high. ddr2_cs 3-0 are decoded memory addr ess lines. each ddr2_cs 3-0 lines select the corresponding external bank. ddr2_data 15-0 i/o/t high-z ddr2 data in/out. connect to corresponding ddr2_data pins. ddr2_dm 1-0 o/t high-z/driven high ddr2 input data mask. mask for the ddr2 write data if driven high. sampled on both edges of ddr2_dqs at ddr2 side. dm0 corresponds to ddr2_data 7C0 and dm1 corresponds to ddr2_data15C8. ddr2_dqs 1-0 ddr2_dqs 1-0 i/o/t (differential) high-z data strobe. output with write data. input with read data. dqs0 corresponds to ddr2_data 7C0 and dqs1 corresponds to ddr2_data 15C8. based on software control via the ddr2ctl3 register, this pin can be single-ended or differential. ddr2_ras o/t high-z/driven high ddr2 row address strobe. connect to ddr2_ras pin, in conjunction with other ddr2 command pins, defines the opera tion for the ddr2 to perform. ddr2_we o/t high-z/driven high ddr2 write enable. connect to ddr2_we pin, in conjunction with other ddr2 command pins, defines the operation for the ddr2 to perform. ddr2_clk0, ddr2_clk0 , ddr2_clk1, ddr2_clk1 o/t (differential) high-z/driven low ddr2 memory clocks. two differential outputs available via software control (ddr2ctl0 register). free running, minimum frequency not guaranteed during reset. ddr2_odt o/t high-z/driven low ddr2 on die termination. odt pin when driven high (along with other require- ments) enables the ddr2 termination resistances. odt is enabled/disabled regardless off read or write commands. table 9. pin descriptions (continued) name type state during/ after reset description the following symbols appear in the type column of table 9 : a = asynchronous, i = input, o = output, s = synchronous, a/d = active drive, o/d = open drain, and t = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. the internal pull-up (ipu) and internal pull-down (ipd) resistors ar e designed to hold the internal path from the pins at the e xpected logic levels. to pull-up or pull-down the external pads to the expected logi c levels, use external resistors. internal pull-up/pull-down resi stors cannot be enabled/disabled and the value of these resistors cannot be prog rammed. the range of an ipu resistor can be between 26kC63k . the range of an ipd resistor can be between 31kC85k . in this table, the ddr2 pins are sstl18 co mpliant. all other pins are lvttl compliant.
rev. pre | page 16 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data dai _p 20C1 i/o/t (ipu) high-z digital applications interface . these pins provide the physical interface to the dai sru. the dai sru configuration registers define the combination of on-chip audio- centric peripheral inputs or outputs conn ected to the pin and to the pins output enable. the configuration registers of these peripherals then determine the exact behavior of the pin. any input or output signal present in the dai sru may be routed to any of these pins. the dai sru provides the connection from the serial ports, the s/pdif module, input data ports (2), and th e precision clock generators (4), to the dai_p20C1 pins. dpi _p 14C1 i/o/t (ipu) high-z digital peripheral interface. these pins provide the physical interface to the dpi sru. the dpi sru configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pins output enable. the configuration registers of these peripherals then determines the exact behavior of the pin. any input or output signal present in the dpi sru may be routed to any of these pins. the dpi sru provides the connec- tion from the timers (2), spis (2), uart (1), flags (12), and general-purpose i/o (9) to the dpi_p14C1 pins. ldat0 7C0 ldat1 7C0 i/o/t (ipd) high-z link port data (link ports 0C1) . when configured as a transmitter, the port drives both the data lines. lclk0 lclk1 i/o/t (ipd) high-z link port clock (link ports 0C1). allows asynchronous data transfers. when configured as a transmitter, the port drives lclkx lines. an external 25k pull-down resistor is required for the proper operation of this pin. lack0 lack1 i/o/t (ipd) high-z link port acknowledge (link port 0C1). provides handshaking. when the link ports are configured as a receiver, the port drives the lackx line. an external 25k pull- down resistor is required for the proper operation of this pin. thd_p i thermal diode anode . if unused, can be left floating. thd_m o thermal diode cathode . if unused, can be left floating. mlbclk 1 i (ipd) media local bus clock. this clock is generated by the mlb controller that is synchro- nized to the most network and provides the timing for the entire mlb interface. 49.152 mhz at fs=48 khz. if unused, can be left floating. mlbdat 1 i/o/t (ipd) in 3 pin mode. i/t (ipd) in 5 pin mode. high-z media local bus data. the mlbdat line is driven by the transmitting mlb device and is received by all other mlb devices including the mlb controller. the mlbdat line carries the actual data. in 5-pin mlb mode, this pin is an input only. if unused, can be left floating. mlbsig 1 i/o/t in 3 pin mode. i/t in 5 pin mode high-z media local bus signal. this is a multiplexed signal which carries the channel/address generated by the mlb controller, as well as the command and rxstatus bytes from mlb devices. in 5-pin mo de, this pin is an input only. if unused, can be left floating. mlbdo 1 o/t (ipd) high-z media local bus data output (in 5 pin mode). this pin is used only in 5-pin mlb mode. this serves as the output data pin in 5- pin mode. if unused, can be left floating. mlbso 1 o/t (ipd) high-z media local bus signal output (in 5 pin mode). this pin is used only in 5-pin mlb mode. this serves as the output signal pin in 5-pin mode. if unused, can be left floating. table 9. pin descriptions (continued) name type state during/ after reset description the following symbols appear in the type column of table 9 : a = asynchronous, i = input, o = output, s = synchronous, a/d = active drive, o/d = open drain, and t = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. the internal pull-up (ipu) and internal pull-down (ipd) resistors ar e designed to hold the internal path from the pins at the e xpected logic levels. to pull-up or pull-down the external pads to the expected logi c levels, use external resistors. internal pull-up/pull-down resi stors cannot be enabled/disabled and the value of these resistors cannot be prog rammed. the range of an ipu resistor can be between 26kC63k . the range of an ipd resistor can be between 31kC85k . in this table, the ddr2 pins are sstl18 co mpliant. all other pins are lvttl compliant.
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 17 of 68 | november 2009 tdi i (ipu) test data input (jtag). provides serial data for the boundary scan logic. tdo o /t high-z test data output (jtag). serial scan output of the boundary scan path. tms i (ipu) test mode select (jtag). used to control the test state machine. tck i test clock (jtag). provides a clock for jtag boundary scan. tck must be asserted (pulsed low) after power-up or held low for proper operation of the device. trst i (ipu) test reset (jtag). resets the test state machine. trst must be asserted (pulsed low) after power-up or held low for proper operation of the processor. emu o/t (ipu) high-z emulation status. must be connected to the adsp-2146x analog devices dsp tools product line of jtag emulators target board connector only. clk_cfg 1C0 i core to clkin ratio control. these pins set the start up clock frequency. note that the operating frequency can be changed by programming the pll multiplier and divider in the pmctl register at any time after the core comes out of reset. the allowed values are: 00 = 6:1 01 = 32:1 10 = 16:1 11 = reserved clkin i local clock in. used in conjunction with xtal. clkin is the clock input. it configures the processors to use either its internal clock generator or an external clock source. connecting the necessary components to clkin and xtal enables the internal clock generator. connecting the external clock to clkin while leaving xtal unconnected configures the processors to use the external clock source such as an external clock oscillator. clkin may not be halted, changed, or operated below the specified frequency. xtal o crystal oscillator terminal. used in conjunction with clkin to drive an external crystal. reset i processor reset. resets the processor to a known state. upon deassertion, there is a 4096 clkin cycle latency for the pll to lock. after this time, the core begins program execution from the hardware reset vector address. the reset input must be asserted (low) at power-up. resetout / runrstin i/o (ipu) reset out/running reset in. the default setting on this pin is reset out. this pin also has a second function as runrstin which is enabled by setting bit 0 of the runrstctl register. for more information, see the adsp-2146x sharc processor hardware reference . boot_cfg 2C0 i boot configuration select. these pins select the boot mode for the processor. the boot_cfg pins must be valid before reset (hardware and software) is de-asserted. 1 the mlb pins are only available on the ad21462w/ad21465w and ad21469w processors. these pins ar e nc (no connect) on the adsp-21 467 and adsp-21469 processors. for more information, see csp_bga ball assignment C adsp-214 62w/adsp-21465w/adsp-2 1469w on page 61 , and csp_bga ball assignment - adsp-21467/adsp- 21469 on page 64 . table 9. pin descriptions (continued) name type state during/ after reset description the following symbols appear in the type column of table 9 : a = asynchronous, i = input, o = output, s = synchronous, a/d = active drive, o/d = open drain, and t = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. the internal pull-up (ipu) and internal pull-down (ipd) resistors ar e designed to hold the internal path from the pins at the e xpected logic levels. to pull-up or pull-down the external pads to the expected logi c levels, use external resistors. internal pull-up/pull-down resi stors cannot be enabled/disabled and the value of these resistors cannot be prog rammed. the range of an ipu resistor can be between 26kC63k . the range of an ipd resistor can be between 31kC85k . in this table, the ddr2 pins are sstl18 co mpliant. all other pins are lvttl compliant.
rev. pre | page 18 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data table 10. pin list, power and ground name type description v dd _ int pi n t e r n a l p o w e r v dd _ ext pe x t e r n a l p o w e r v dd _ a pa n a l o g p o w e r f o r p l l v dd _ thd pt h e r m a l d i o d e p o w e r v dd _ ddr 2 1 pd d r 2 i n t e r f a c e p o w e r v ref ddr2 input voltage reference gnd g ground agnd g analog ground 1 applies to ddr2 signals.
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 19 of 68 | november 2009 specifications operating conditions 450 mhz 400 mhz unit parameter 1 1 specifications subject to change without notice. description min max min max v dd _ int internal (core) supply voltage 1.05 1.15 tbd 2 2 the expected nominal value is 1.05 v and in itial customer designs should design with a programmable regulator that can be adjus ted from 0.95 v to 1.15 v +/-50mv tbd 2 v v dd _ ext external (i/o) supply voltage 3.13 3.47 3.13 3.47 v v dd _ a 3 3 see figure 3 on page 12 for an example filter circuit. analog power supply voltage 1.05 1.15 tbd 2 tbd 2 v v dd _ ddr 2 4, 5 4 applies to ddr2 signals. 5 if unused, see unused ddr2 pins on page 14 . ddr2 controller supply voltage 1.7 1.9 1.7 1.9 v v dd _ thd thermal diode supply voltage 3.13 3.47 3.13 3.47 v v ref ddr2 reference voltage 0.84 0.96 0.84 0.96 v v ih 6 6 applies to input and bidirectional pins: ami_addr23C0, ami_data7C0 , flag3C0, dai_px, dpi_px, spids , bootcfgx, clkcfgx, (runrstin ), reset , tck, tms, tdi, trst . high level input voltage @ v dd _ ext = max 2.0 v dd _ ext + 0.5 2.0 v dd _ ext + 0.5 v v il 6 low level input voltage @ v dd _ ext = min C0.3 0.8 C0.3 0.8 v v ih _ clkin 7 7 applies to input pin clkin. high level input voltage @ v dd _ ext = max 2.0 v dd _ ext + 0.5 2.0 v dd _ ext + 0.5 v v il _ clkin 7 low level input voltage @ v dd _ ext = min C0.5 1.32 C0.5 1.32 v v il _ ddr 2 (dc) dc low level input voltage -0.3 v ref C 0.12 -0.3 v ref C 0.12 v v ih _ ddr 2 (dc) dc high level input voltage v ref + 0.13 v dd _ ddr 2 + 0.3 v ref + 0.13 v dd _ ddr 2 + 0.3 v v il _ ddr 2 (ac) ac low level input voltage v ref C 250 v ref C 250 mv v ih _ ddr 2 (ac) ac high level input voltage v ref + 250 v ref + 250 mv t j junction temperature 324-lead csp_bga @ t ambient 0 c to +70 c 0 125 0 tbd c t j junction temperature 324-lead csp_bga @ t ambient C40 c to +85 c n/a n/a C40 tbd c
rev. pre | page 20 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data electrical characteristics 450 mhz 400 mhz unit parameter 1 description test conditions min typical max min typical max v oh 2 high level output voltage @ v dd _ ext = min, i oh = C1.0 ma 3 2.4 2.4 v v ol 2 low level output voltage @ v dd _ ext = min, i ol = 1.0 ma 3 0.4 0.4 v v oh _ ddr 2 high level output voltage for ddr2 @ v dd _ ddr = min, ioh = C13.4 ma 1.4 1.4 v v ol _ ddr 2 low level output voltage for ddr2 @ v dd _ ddr = min, iol = 13.4 ma 0.29 0.29 v i ih 4, 5 high level input current @ v dd _ ext = max, v in = v dd _ ext max 10 10 a i il 4 low level input current @ v dd _ ext = max, v in = 0 v 10 10 a i ilpu 5 low level input current pull-up @ v dd _ ext = max, v in = 0 v 200 200 a i ihpd 6 high level input current pull-down @ v dd _ ext = max, v in = v dd _ ext max 200 200 a i ozh 7, 8 three-state leakage current @ v dd _ ext = max, v in = v dd _ ext max 10 10 a i ozl 7 three-state leakage current @ v dd _ ext = max, v in = 0 v 10 10 a i ozlpu 8 three-state leakage current pull-up @ v dd _ ext = max, v in = 0 v 200 200 a i ozlpd 9 three-state leakage current pull-down @ v dd _ ext = max, v in = v dd _ ext max 200 200 a i dd - intyp 10, 11 supply current (internal) tbd tbd tbd ma c in 12, 13 input capacitance tbd tbd tbd pf 1 specifications subject to change without notice. 2 applies to output and bid irectional pins: ami_addr23-0, ami_data7-0, ami_rd , ami_wr , flag3C0, dai_px, dpi_px, emu , tdo. 3 see output drive currents on page 59 for typical drive current capabilities. 4 applies to input pins: bootcfgx, clkcfgx, tck, reset , clkin. 5 applies to input pins with internal pull-ups: trst , tms, tdi. 6 applies to input pins with internal pull-downs: mlbclk 7 applies to three-statab le pins: all ddr2 pins. 8 applies to three-statable pins with pull-ups: dai_px, dpi_px, emu . 9 applies to three-statable pins with pull-do wns: mlbclk, mlbdat, mlbsig, mlbdo, mlbso, ldat07-0, ldat17-0, lclk0, lclk1, lack0, lack1. 10 typical internal current data reflec ts nominal operating conditions. 11 see engineer-to-engineer note estimatin g power dissipation for ad sp-2146x sharc proc essors for further information. 12 applies to all signal pins. 13 guaranteed, but not tested.
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 21 of 68 | november 2009 package information the information presented in figure 4 provides details about the package branding for the adsp-2146x processors. for a complete listing of pr oduct availability, see ordering guide on page 68 . esd sensitivity power dissipation see table 12 and engineer-to-engineer note estimating power dissipation for adsp-2146x shar c processors for detailed thermal and power information regarding maximum power dis- sipation. for information on package thermal specifications, see thermal characteri stics on page 60 . absolute maximum ratings stresses greater than those listed in table 13 may cause perma- nent damage to the device. these are stress ratings only; functional operation of the device at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. timing specifications use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the va lues given in this data sheet reflect statistical variations and worst cases. consequently, it is not meaningful to add parameters to derive longer times. see figure 46 on page 59 under test conditions for voltage refer- ence levels. switching characteristics specify how the processor changes its signals. circuitry external to the processor must be designed for compatibility with these signal characteristics. switching char- acteristics describe what the processor will do in a given circumstance. use switching charac teristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. core clock requirements the processors internal clock (a multiple of clkin) provides the clock signal for timing inte rnal memory, processor core, and serial ports. during reset, prog ram the ratio between the proces- sors internal clock frequency and external (clkin) clock frequency with the clk_cfg1C0 pins. figure 4. typical package brand table 11. package br and information brand key field description t temperature range pp package type z rohs compliant option cc see ordering guide vvvvvv.x assembly lot code n.n silicon revision # rohs compliant designation yyww date code table 12. power dissipation parameter min typ max unit typical activity at 1.0 v, t j = 125 c 682 mw vvvvvv.x n.n tppz-cc s s a esd (electrostatic discharge) sensitive device. charged devices and circuit boards can discharge without detection. although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy esd. therefore, proper esd precautions should be taken to avoid performance degradation or loss of functionality. table . absolute aimum atings parameter rating internal (core) supply voltage (v dd _ int ) C0.3 v to +1.32 v analog (pll) supply voltage (v dd _ a ) C0.3 v to +1.15 v external (i/o) supply voltage (v dd _ ext )C0.3 v to +4.6 v thermal diode supply voltage (v dd _ thd )C0.3 v to +4.6 v ddr2 controller supply voltage (v dd _ ddr 2) C0.3 v to +2.7 v ddr2 input voltage C0.5 v to +2.7 v input voltage C0.5 v to +3.8 v output voltage swing C0.5 v to v dd_ext +0.5 v load capacitance 200 pf storage temperature range C65 c to +150 c junction temperature under bias 125 c
rev. pre | page 22 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data the processors internal clock sw itches at higher frequencies than the system input clock (clk in). to generate the internal clock, the processor uses an internal phase-locked loop (pll, see figure 5 ). this pll-based clocking minimizes the skew between the system clock (clkin ) signal and the processors internal clock. voltage controlled oscillator in application designs, the p ll multiplier value should be selected in such a way that the vco frequency never exceeds f vco specified in table 16 . ? the product of clkin and pllm must never exceed 1/2 of f vco (max) in table 16 if the input divider is not enabled (indiv = 0). ? the product of clkin and pllm must never exceed f vco (max) in table 16 if the input divider is enabled (indiv = 1). the vco frequency is calculated as follows: f vco = 2 pllm f input f cclk = (2 pllm f input ) ( plld ) where: f vco = vco output pllm = multiplier value programm ed in the pmctl register. during reset, the pllm value is derived from the ratio selected using the clk_cfg pins in hardware. plld = divider value 2, 4, 8, or 16 based on the plld value programmed on the pmctl regist er. during reset this value is 2. f input = is the input frequency to the pll. f input = clkin when the input divider is disabled or f input = clkin 2 when the input divider is enabled note the definitions of the clock periods that are a function of clkin and the appropriate ra tio control shown in and table 14 . all of the timing specif ications for the adsp-2146x peripherals are define d in relation to t pclk . see the peripheral specific section for each peri pherals timing information. figure 5 shows core to clkin relati onships with external oscil- lator or crystal. the shaded di vider/multiplier blocks denote where clock ratios can be set through hardware or software using the power management control register (pmctl). for more information, see the adsp-2146x sharc processor hard- ware reference. table 14. clock periods timing requirements description t ck clkin clock period t cclk processor core clock period t pclk peripheral clock period = 2 t cclk figure 5. core clock and system clock relationship to clkin loop filter clkin pclk ddr2_clk ddr2 divider b yp a s s mu x divide by 2 cclk by p a s s m u x pll xtal clkin divider resetout reset u co u i c diider c_cxmctxm imu resetout couttesto dea o ci cces corerst cc c c_cx mct iort coc diider c a s s m u mct mct mct idi mct cr mct ddrcr mct d mutiier iut cc
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 23 of 68 | november 2009 power-up sequencing the timing requirements for pr ocessor startup are given in table 15 . while no specific power-up sequencing is required between v dd _ ext , v dd _ ddr 2 , and v dd _ int , there are some consider- ations that the system design s should take into account. ? no power supply should be powered up for an extended period of time (> 200 ms) befo re another supply starts to ramp up. ?if v dd _ int power supply comes up after v dd _ ext , any pin, such as resetout and reset may actually drive momentarily until the v dd _ int rail has powered up. systems sharing these signals on the bo ard must determine if there are any issues that need to be addressed based on this behavior. note that during power-up, when the v dd _ int power supply comes up after v dd _ ext , a leakage current of the order of three- state leakage current pull-up, pu ll-down, may be observed on any pin, even if that is an in put only (for example the reset pin) until the v dd _ int rail has powered up. table 15. power up sequencing timing requirements (processor startup) parameter min max unit timing requirements t rstvdd reset low before v dd _ int or v dd _ ext or v dd _ ddr 2 on 0 ms t ivdd - evdd v dd _ int on before v dd _ ext C200 +200 ms t evdd _ ddr 2 vdd v dd _ ext on before v dd _ ddr 2 C200 +200 ms t clkvdd 1 clkin valid after v dd _ int or v dd _ ext or v dd _ ddr 2 valid 0 200 ms t clkrst clkin valid before reset deasserted 10 2 ms t pllrst pll control setup before reset deasserted 20 3 ms switching characteristic t corerst core reset deasserted after reset deasserted 4096 t ck + 2 t cclk 4, 5 ms 1 valid v dd _ int assumes that the supply is fully ramped to its nominal value. voltage ra mp rates can vary from micros econds to hund reds of mil liseconds depending on the design of the powe r supply subsystem. 2 assumes a stable clkin signal, after meeting worst-case startup timing of crystal os cillators. refer to your crystal oscillator manufacturer's datasheet for startup time. assume a 25 ms maximum oscillator startup time if using the xtal pin an d internal oscillator circuit in conjunction with an external c rystal. 3 based on clkin cycles. 4 applies after the power-up sequence is complete. subsequent resets require a minimum of four clkin cycles for reset to be held low in order to properly initialize and propagate default states at all i/o pins. 5 the 4096 cycle count depends on t srst specification in table 17 . if setup time is not met, one additional clkin cycle may be added to the core reset time, resulting in 4097 cycles maximum.
rev. pre | page 24 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data figure 6. power-up sequencing t rstvdd t ivdd - evdd t evdd - ddr2vdd t clkvdd t clkrst t corerst t pllrst v dd_ext v dd_ddr2 v dd_int clkin clk_cfg1C0 reset resetout
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 25 of 68 | november 2009 clock input clock signals the adsp-2146x can use an external clock or a crystal. see the clkin pin description in table 9 . programs can configure the processor to use its internal cl ock generator by connecting the necessary components to clkin and xtal. figure 8 shows the component connections used for a crystal operating in funda- mental mode. note that the cloc k rate is achieved using a 25.000 mhz crystal and a pll multiplier ratio 16:1 (cclk:clkin achieves a clock speed of 400 mhz). to achieve the full core clock rate, programs need to configure the multiplier bits in the pmctl register. in case of the adsp- 21462w, adsp-21465w, and adsp-21469w, the maximum clock speed of 400 mhz is arrived at by using a 25 mhz crystal with the default multiplier of 16:1. table 16. clock input parameter 400 mhz 1 1 applies to all 40 0 mhz models. see ordering guide on page 68 . unit min max timing requirements t ck clkin period 15 2 2 applies only for clk_cfg1C0 = 00 and defa ult values for pll control bits in pmctl. 100 ns t ckl clkin width low 7.5 1 45 ns t ckh clkin width high 7.5 1 45 ns t ckrf clkin rise/fall (0.4 v to 2.0 v) 3 ns t cclk 3 3 any changes to pll control bits in the pmctl regis ter must meet core clock timing specification t cclk . cclk period 2.5 6 10 ns f vco 4 4 see figure 5 on page 22 for vco diagram. vco frequency 200 2000 t cclk mhz t ckj 5, 6 5 actual input jitter should be combined with ac specifications for acc urate timing analysis. 6 jitter specification is maximum peak-to -peak time interval error (tie) jitter. clkin jitter tolerance C250 +250 ps figure 7. clock input clkin t ck t ckl t ckh j figure 8. 450 mhz operation (fundamental mode crystal) c1 22pf y1 r1 1m * xtal clkin c2 22pf 25.000 mhz r2 47 * r2 should be chosen to limit crystal drive power. refer to crystal manufacturers specifications *typical values adsp-2146x
rev. pre | page 26 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data reset running reset the following timing specification applies to resetout /runrstin pin when it is configured as runrstin . table 17. reset parameter min max unit timing requirements t wrst 1 reset pulse width low 4 t ck ns t srst reset setup before clkin low 8 ns 1 applies after the power-up sequence is complete. at power-up, th e processors internal phase-locked loop requires no more than 1 00 m s while reset is low, assuming stable v dd and clkin (not including start-up time of external clock oscillator). figure 9. reset clkin reset srst w table 18. running reset parameter min max unit timing requirements t wrunrst running reset pulse width low 4 t ck ns t srunrst running reset setup before clkin high 8 ns figure 10. running reset clkin runrstin t w
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 27 of 68 | november 2009 interrupts the following timing specification applies to the flag0, flag1, and flag2 pins when they are config ured as irq0 , irq1 , and irq2 interrupts as well as the dai_p20C1 and dpi_p14C1 pins when they ar e configured as interrupts. core timer the following timing specification applies to flag3 when it is configured as the core timer (tmrexp). table 19. interrupts parameter min max unit timing requirement t ipw irqx pulse width 2 t pclk + 2 ns figure 11. interrupts da 4 a (q) w table 20. core timer parameter min max unit switching characteristic t wctim tmrexp pulse width 4 t pclk C 1 ns figure 12. core timer fla3 (m) wm
rev. pre | page 28 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data timer pwm_out cycle timing the following timing specification applies to timer0 and timer1 in pwm_out (pulse-width modulation) mode. timer signals are routed to the dpi_p 14C1 pins through the dpi sru. therefore, the timing specificatio ns provided below are valid at the dpi_p14C1 pins. timer wdth_cap timing the following timing specification applies to timer0 and timer1, and in wdth_cap (pulse widt h count and capture) mode. timer signals are routed to the dpi_p14C1 pins through the sru. therefore, the timing specification provided below is valid at the dpi_p14C1 pins. table 21. timer pwm_out timing parameter min max unit switching characteristic t pwmo timer pulse width output 2 t pclk C 1.2 2 (2 31 C 1) t pclk ns figure 13. timer pwm_out timing dpi_p14 (m) wm table 22. timer width capture timing parameter min max unit timing requirement t pwi timer pulse width 2 t pclk 2 (2 31 C 1) t pclk ns figure 14. timer width capture timing dpi_p14 (m) w
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 29 of 68 | november 2009 pin to pin direct routing (dai and dpi) for direct pin connections only (for example dai_pb01_i to dai_pb02_o). table 23. dai and dpi pin to pin routing parameter min max unit timing requirement t dpio delay dai/dpi pin input valid to dai/dpi output valid 1.5 12 ns figure 15. dai and dpi pin to pin direct routing dan n am m
rev. pre | page 30 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data precision clock generator (direct pin routing) this timing is only valid when the sru is configured such that the precision clock generator (pcg) takes its inputs directly from the dai pins (via pin buffers) and sends its outputs directly to the dai pins. for the other ca ses, where the pcgs inputs and outputs are not directly routed to/from dai pins (via pin buffers) there is no timing data available. all timing param- eters and switching characteristics apply to external dai pins (dai_p01 C dai_p20). table 24. precision clock generator (direct pin routing) parameter min max unit timing requirement s t pcgiw input clock period t pclk 4 ns t strig pcg trigger setup before falling edge of pcg input clock 4.5 ns t htrig pcg trigger hold after falling edge of pcg input clock 3ns switching characteristics t dpcgio pcg output clock and frame sync active edge delay after pcg input clock 2.5 10 ns t dtrigclk pcg output clock delay after pcg trigger 2.5 + (2.5 t pcgip ) 10 + (2.5 t pcgip )n s t dtrigfs pcg frame sync delay after pcg trigger 2.5 + ((2.5 + d C ph) t pcgip ) 10 + ((2.5 + d C ph) t pcgip )ns t pcgow 1 output clock period 2 t pcgip C 1 ns d = fsxdiv, ph = fsxphase. for more information, see the adsp-214 6x sharc processor hardware reference, precision clock genera tors chapter. 1 normal mode of operation. figure 16. precision clock generator (direct pin routing) dan n x am m x () ay y x az z x h w w
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 31 of 68 | november 2009 flags the timing specifications provided below apply to ami_addr23C0 and ami_data7C0 when configured as flags. see table 9 on page 14 for more information on flag use. table 25. flags parameter min max unit timing requirement t fipw dpi_p14C1, ami_addr23C0, ami_data7C0, flag3C0 in pulse width 2 t pclk + 3 ns switching characteristic t fopw dpi_p14C1, ami_addr23C0, ami_data7C0, flag3C0 out pulse width 2 t pclk C 1.5 ns figure 17. flags dpi_p14 (a3 ) (amaa7) (ama3) 4 (a3 ) (amaa7) (ama3) w w
rev. pre | page 32 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data ddr2 sdram read cycle timing table 26. ddr2 sdram read cycle timing, v dd-ddr2 nominal 1.8v parameter min max unit timing requirements t ac dq output access time from ck/ck C1.0 0.7 ns t dqsck dqs output access time from ck/ck C1.0 0.7 ns t dqsq dqs-dq skew for dqs and associated dq signals 0.450 ns t qh dq, dqs output hold time from dqs 1.5 ns t rpre read preamble 0.25 t ck t rpst read postamble 0.25 t ck switching characteristics t ck clock cycle time, cl= x 5 ns t ch minimum clock pulse width 2.35 2.65 ns t cl maximum clock pulse width 2.35 2.65 ns t as address setup time 2.6 ns t ah address hold time 1.0 ns figure 18. ddr2 sdram controller input ac timing ddr2_clk ddr2_dqs t ac (max) t rpre t dqsq t dqsq t q t q t rpst ddr2_data ddr2_clk t dqsck (min) ddr2_dqs t dqsck (max) t ac (min)
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 33 of 68 | november 2009 ddr2 sdram write cycle timing table 27. ddr2 sdram read cycle timing, v dd-ddr2 nominal 1.8v parameter min max unit switching characteristics t ck clock cycle time 5 ns t ch minimum clock pulse width 2.35 2.65 ns t cl maximum clock pulse width 2.35 2.65 ns t dqss 1 1 write command to first dqs delay = wl t ck + t dqss . dqs latching rising transitions to associated clock edges 0 0.20 ns t ds last data valid to dqs delay 1.0 ns t dh dqs to first data invalid delay 0.95 ns t dss dqs falling edge to clock setup time 2.35 ns t dsh dqs falling edge hold time from ck 2.60 ns t dqsh dqs input high pulse width 0.48 t ck t dqsl dqs input low pulse width 0.48 t ck t wpre write preamble 0.8 t ck t wpst write postamble 0.5 t ck t as control/address maximum delay from ddck rise 2.6 ns t ah control/address minimum delay from ddck rise 1.0 ns figure 19. ddr2 sdram controller output ac timing ck dq q/m a a ah h q h w q qh w q
rev. pre | page 34 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data memory read bus master use these specifications for asyn chronous interfacing to memo- ries. note that timing fo r ami_ack, ami_data, ami_rd , ami_wr , and strobe timing parameters only apply to asyn- chronous access mode. table 28. memory read bus master parameter min max unit timing requirements t dad address, selects delay to data valid 1, 2 w + t ddr 2_ clk C5.12 ns t drld ami_rd low to data valid 1 w C 3.2 ns t sds data setup to ami_rd high 2.5 ns t hdrh data hold from ami_rd high 3, 4 0n s t daak ami_ack delay from address, selects 2, 5 t ddr 2_ clk C9.5 + w ns t dsak ami_ack delay from ami_rd low 4 w C 7.0 ns switching characteristics t drha address selects hold after ami_rd high rh + 0.20 ns t darl address selects to ami_rd low 2 t ddr 2_ clk C 3.3 ns t rw ami_rd pulse width w C 1.4 ns t rwr 6 ami_rd high to ami_rd low hi + t ddr 2_ clk C 0.8 ns w = (number of wait states specified in amictlx register) t ddr 2_ clk . hi = rhc + ic (rhc = (number of read hold cycles specified in amictlx register) x t ddr 2_ clk ic = (number of idle cycles sp ecified in amictlx register) x t ddr 2_ clk ). h = (number of hold cycles specified in amictlx register) x t ddr 2_ clk . 1 data delay/setup: system must meet t dad , t drld , or t sds. 2 the falling edge of ami_ms x, is referenced. 3 note that timing for ami_ack, ami_data, ami_rd , ami_wr , and strobe timing parameters only apply to asynchronous access mode. 4 data hold: user must meet t hdrh in asynchronous access mode. see test conditions on page 59 for the calculation of hold time s given capacitive and dc loads. 5 ami_ack delay/setup: user must meet t daak , or t dsak , for deassertion of ami_ack (low). for asynchronous assertion of ami_ack (high) user must meet t daak or t dsak . 6 for read to read: same bank = (1 + rhc ) ddr2clk if ic is not programmed. for read to read: different bank = t rwr . for read to write: 5 ddr2clk cycles + (ic C 4), at least 5 ddr2clk cycles for both the same bank and different banks.
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 35 of 68 | november 2009 figure 20. memory readbus master ami_ack ami_data t drha t rw t hdrh t rwr t dad t darl t drld t sds t dsak t daak ami_wr ami_rd ami_addr ami_msx
rev. pre | page 36 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data memory write bus master use these specifications for asyn chronous interfacing to memo- ries. note that timing fo r ami_ack, ami_data, ami_rd , ami_wr , and strobe timing parameters only apply to asyn- chronous access mode. table 29. memory write bus master parameter min max unit timing requirements t daak ami_ack delay from address, selects 1, 2 t ddr 2_ clk C 9.7 + w ns t dsak ami_ack delay from ami_wr low 1, 3 w C 4.9 ns switching characteristics t dawh address, selects to ami_wr deasserted 2 t ddr 2_ clk C3.1+ w ns t dawl address, selects to ami_wr low 2 t ddr 2_ clk C2.7 ns t ww ami_wr pulse width w C 1.3 ns t ddwh data setup before ami_wr high t ddr 2_ clk C3.0+ w ns t dwha address hold after ami_wr deasserted h + 0.15 ns t dwhd data hold after ami_wr deasserted h + 0.02 ns t datrwh data disable after ami_wr deasserted 4 t ddr 2_ clk C 1.37 + h t ddr 2_ clk + 4.9+ h ns t wwr ami_wr high to ami_wr low 5 t ddr 2_ clk C1.5+ h ns t ddwr data disable before ami_rd low 2t ddr 2_ clk C 4.11 ns t wde ami_wr low to data enabled t ddr 2_ clk C 3.5 ns w = (number of wait states specified in amictlx register) t sddr 2_ clk h = (number of hold cycles sp ecified in amictlx register) x t ddr 2_ clk 1 ami_ack delay/setup: system must meet t daak , or t dsak , for deassertion of ami_ack (low). for asynchronou s assertion of ami_ack (high) user must meet t daak or t dsak . 2 the falling edge of ami_msx is referenced. 3 note that timing for ami_ack, ami_data, ami_rd , ami_wr , and strobe timing parameters only applies to asynchronous access mode. 4 see test conditions on page 59 for calculation of hold times given capacitive and dc loads. 5 for write to write: 1 + hc, for both same bank and different bank. for write to read: 3 ddr2clk cycles + hc , for the same bank and different banks. figure 21. memory write bus master ami_ck i_dt t d t d t r t dtr t dd t t ddr t dd t dl t de t dsk t dk i_rd i_r ami_addr ami_msx
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 37 of 68 | november 2009 link ports calculation of link receiver data setup and hold relative to link clock is required to determin e the maximum allowable skew that can be introduced in the transmission path between ldata and lclk. setup skew is the maximum delay that can be introduced in ldata relative to lclk: (setup skew = t lclktwh min C t dldch C t sldcl ). hold skew is the maximum delay that can be introduced in lclk relative to ldata, (hold skew = t lclktwl min C t hldch C t hldcl ). calculations made directly from speed specifications will result in unrealistically small skew time s because they include multiple tester guardbands. the setup an d hold skew times shown below are calculated to include only one tester guardband. setup skew = tbd ns max hold skew = tbd ns max note that there is a two-cycle effect latency between the link port enable instruction and the li nk port actually being enabled by the processor. table 30. link ports C receive parameter min max unit timing requirements t sldcl data setup before lclk low 0.5 ns t hldcl data hold after lclk low 1.5 ns t lclkiw lclk period t lclk (6ns) ns t lclkrwl lclk width low 2.6 ns t lclkrwh lclk width high 2.6 ns switching characteristics t dlalc lack low delay after lclk low 1 51 2n s 1 lack goes low with t dlalc relative to rise of lclk after first byte, but does not go low if the receiver's link buffer is not about to fill. figure 22. link portsreceive lda7 a() a h wh w w
rev. pre | page 38 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data table 31. link ports C transmit parameter min max unit timing requirements t slach lack setup before lclk low 8.5 ns t hlach lack hold after lclk low C3 ns switching characteristics t dldch data delay after lclk high 1 ns t hldch data hold after lclk high 0 ns t lclktwl lclk width low 0.5 t lclk C 0.1 0.6 t lclk + 0.1 1 ns t lclktwh lclk width high 0.4 t lclk C 0.1 1 0.5 t lclk + 0.1 ns t dlaclk lclk low delay after lack high 4 t lclk + 8 ns 1 for 1:2.5 ratio. for other ratios this specification is 0.5 t lclk figure 23. link portstransmit lclk ldt7C0 lck (in) out t dldc t ldc t slc t lc t dlclk t lclkt t lclktl lst byte transmitted first byte transmitted lclk inactive (high) notes 1. the t slach requirement applies to the rising edge of lclk only for the first byte transmitted.
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 39 of 68 | november 2009 serial ports to determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) serial clock (sclk) width. serial port signals are routed to the dai_p20C1 pins using the sru. therefore, the timing spec ifications provided below are valid at the dai_p20C1 pins. table 32. serial portsexternal clock parameter min max unit timing requirements t sfse 1 frame sync setup before sclk (externally generated frame sync in either transmit or receive mode) 2.5 ns t hfse 1 frame sync hold after sclk (externally generated frame sync in either transmit or receive mode) 2.5 ns t sdre 1 receive data setup before receive sclk 1.9 ns t hdre 1 receive data hold after sclk 2.5 ns t sclkw sclk width (t pclk 4) 2 C 0.5 ns t sclk sclk period t pclk 4 ns switching characteristics t dfse 2 frame sync delay after sclk (internally generated frame sync in either transmit or receive mode) 10.25 ns t hofse 2 frame sync hold after sclk (internally generated frame sync in either transmit or receive mode) 2 ns t ddte 2 transmit data delay after transmit sclk 7.8 ns t hdte 2 transmit data hold after transmit sclk 2 ns 1 referenced to sample edge. 2 referenced to drive edge. table 33. serial portsinternal clock parameter min max unit timing requirements t sfsi 1 frame sync setup before sclk (externally generated frame sync in either transmit or receive mode) 7 ns t hfsi 1 frame sync hold after sclk (externally generated frame sync in either transmit or receive mode) 2.5 ns t sdri 1 receive data setup before sclk 7 ns t hdri 1 receive data hold after sclk 2.5 ns switching characteristics t dfsi 2 frame sync delay after sclk (internally generated frame sync in transmit mode) 4 ns t hofsi 2 frame sync hold after sclk (internally generated frame sync in transmit mode) C1.0 ns t dfsir 2 frame sync delay after sclk (internally generated frame sync in receive mode) 9.75 ns t hofsir 2 frame sync hold after sclk (internally generated frame sync in receive mode) C1.0 ns t ddti 2 transmit data delay after sclk 3.25 ns t hdti 2 transmit data hold after sclk C1.0 ns t sckliw transmit or receive sclk width 2 t pclk C 1.5 2 t pclk + 1.5 ns 1 referenced to the sample edge. 2 referenced to drive edge.
rev. pre | page 40 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data table 34. serial portsenable and three-state parameter min max unit switching characteristics t ddten 1 data enable from external transmit sclk 2 ns t ddtte 1 data disable from external transmit sclk 10 ns t ddtin 1 data enable from internal transmit sclk C1 ns 1 referenced to drive edge. table 35. serial portsexternal late frame sync parameter min max unit switching characteristics t ddtlfse 1 data delay from late external transmit frame sync or external receive frame sync with mce = 1, mfd = 0 7.75 ns t ddtenfs 1 data enable for mce = 1, mfd = 0 0.5 ns 1 the t ddtlfse and t ddtenfs parameters apply to left-justified as well as dsp serial mode, and mce = 1, mfd = 0. figure 24. external late frame sync 1 1 this figure reflects changes made to support left -justified mode. drive sple externl receive fs it ce = 1, mfd = 0 2nd bit dai_p20C1 (sclk) dai_p20C1 (frame sync) dai_p20C1 (data channel a/b) 1st bit drive t ddte/i t hdte/i t ddtlfse t ddtenfs t sfse/i drive sample late external transmit fs 2nd bit dai_p20C1 (sclk) dai_p20C1 (frame sync) dai_p20C1 (data channel a/b) 1st bit drive t ddte/i t hdte/i t ddtlfse t ddtenfs t sfse/i t hfse/i t hfse/i notes
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 41 of 68 | november 2009 figure 25. serial ports drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (frame sync) dai_p20C1 (sclk) t hofsir t hfsi t hdri data receiveinternal clock drive edge drive edge drive edge drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (sclk) dai_p20C1 (data channel a/b) dai_p20C1 (frame sync) dai_p20C1 (sclk, ext) sclk dai_p20C1 (sclk) t hfsi t ddti data transmitinternal clock drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (frame sync) dai_p20C1 (sclk) t hofse t hofsi t hdti t hfse t hdte t ddte data transmitexternal clock drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (frame sync) dai_p20C1 (sclk) t hofse t hfse t hdre data receiveexternal clock notes 1. either the rising edge or the falling edge of sclk (external or internal) can be used as the active sampling edge. notes 1. either the rising edge or the falling edge of sclk (external or internal) can be used as the active sampling edge. t sclkiw t dfsir t sfsi t sdri t sclkw t dfse t sfse t sdre t dfse t sfse t sfsi t dfsi t sclkiw t ddtin t ddten t ddtte t sclkw
rev. pre | page 42 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data input data port (idp) the timing requirements for the idp are given in table 36 . idp signals are routed to the dai_p20C1 pins using the sru. there- fore, the timing specifications provided below are valid at the dai_p20C1 pins. table 36. input data port (idp) parameter min max unit timing requirements t sisfs 1 frame sync setup before serial clock rising edge 4 ns t sihfs 1 frame sync hold after serial clock rising edge 2.5 ns t sisd 1 data setup before serial clock rising edge 2.5 ns t sihd 1 data hold after serial clock rising edge 2.5 ns t idpclkw clock width (t pclk 4) 2 C 1 ns t idpclk clock period t pclk 4 ns 1 the serial clock, data and frame sync signals can come from a ny of the dai pins. the serial clock and frame sync signals can a lso come via pcg or sports. pcg's input can be either clkin or any of the dai pins. figure 26. idp master timing da (a) am a (amy) a (aa) w h h
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 43 of 68 | november 2009 parallel data acquisition port (pdap) the timing requirements for the pdap are provided in table 37 . pdap is the parallel mode operation of channel 0 of the idp. for details on the operation of the pdap, see the pdap chapter of the adsp-2146x sharc processor hardware reference . note that the 20-bits of external pdap data can be provided through the ami_addr 23C4 pins or over the dai pins. table 37. parallel data acquisition port (pdap) parameter min max unit timing requirements t sphold 1 pdap_hold setup before pdap_clk sample edge 2.5 ns t hphold 1 pdap_hold hold after pdap_clk sample edge 2.5 ns t pdsd 1 pdap_dat setup before serial clock pdap_clk sample edge 3.85 ns t pdhd 1 pdap_dat hold after serial clock pdap_clk sample edge 2.5 ns t pdclkw clock width (t pclk 4) 2 C 3 ns t pdclk clock period t pclk 4 ns switching characteristics t pdhldd delay of pdap strobe after last pdap_clk capture edge for a word 2 t pclk + 3 ns t pdstrb pdap strobe pulse width 2 t pclk C 1 ns 1 data source pins are ami_addr23C4 or dai pins. source pins for serial clock and frame sync are: 1) ami_addr3C2 pins, 2) dai pi ns. figure 27. pdap timing dai_p20C1/addr3 (pdap_clk) sample edge dai_p20C1 (pdap_hold) dai_p20C1 (pdap_strobe) t pdstrb t pdhldd t pdhd t pdsd t sphold t hphold t pdclk t pdclkw dai_p20C1/addr23C4 (pdap_data)
rev. pre | page 44 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data sample rate converterserial input port the asrc input signals are rout ed from the dai_p20C1 pins using the sru. therefore, the timi ng specifications provided in table 38 are valid at the dai_p20C1 pins. table 38. asrc, serial input port parameter min max unit timing requirements t srcsfs 1 frame sync setup before serial clock rising edge 4 ns t srchfs 1 frame sync hold after serial clock rising edge 5.5 ns t srcsd 1 data setup before serial clock rising edge 4 ns t srchd 1 data hold after serial clock rising edge 5.5 ns t srcclkw clock width (t pclk 4) 2 C 1 ns t srcclk clock period t pclk 4 ns 1 the serial clock, data and frame sync signals can come from any of the dai pins. the serial clock and frame sync signals can a lso come via pcg or sports. pcgs input can be either clkin or any of the dai pins. figure 28. asrc serial input port timing da (a) am a (amy) a (aa) w h h
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 45 of 68 | november 2009 sample rate converterserial output port for the serial output port, the frame-sync is an input and it should meet setup and hold times with regard to the serial clock on the output port. the serial data output, has a hold time and delay specification with regard to serial clock. note that serial clock rising edge is the sampling edge and the falling edge is the drive edge. table 39. asrc, serial output port parameter min max unit timing requirements t srcsfs 1 frame sync setup before serial clock rising edge 4 ns t srchfs 1 frame sync hold after serial clock rising edge 5.5 ns t srcclkw clock width (t pclk 4) 2 C 1 ns t srcclk clock period t pclk 4 ns switching characteristics t srctdd 1 transmit data delay after serial clock falling edge 9.9 ns t srctdh 1 transmit data hold after serial clock falling edge 1 ns 1 the serial clock, data and frame sync signals can come from a ny of the dai pins. the serial clock and frame sync signals can a lso come via pcg or sports. pcgs input can be either clkin or any of the dai pins. figure 29. asrc serial output port timing da (a) am a (amy) a (aa) w h h
rev. pre | page 46 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data pulse-width modulation generators (pwm) the following timing specifications apply when the ami_addr23C8 pins are configured as pwm. table 40. pulse-width modulation (pwm) timing parameter min max unit switching characteristics t pwmw pwm output pulse width t pclk C 2 (2 16 C 2) t pclk C 2 ns t pwmp pwm output period 2 t pclk C 1.5 (2 16 C 1) t pclk C 1.5 ns figure 30. pwm timing pwm wmw wm
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 47 of 68 | november 2009 s/pdif transmitter serial data input to the s/pdif transmitter can be formatted as left-justified, i 2 s, or right-justified with word widths of 16-, 18-, 20-, or 24-bits. the following se ctions provide timing for the transmitter. s/pdif transmitter-serial input waveforms figure 31 shows the right-justified mo de. lrclk is high for the left channel and low fo r the right channel. data is valid on the rising edge of serial clock. the msb is delayed 12-bit clock periods (in 20-bit output mode) or 16-bit clock periods (in 16- bit output mode) from an lrclk transition, so that when there are 64 serial clock periods per lrclk period, the lsb of the data will be right-justified to the next lrclk transition. figure 32 shows the default i 2 s-justified mode. lrclk is low for the left channel and hi for the right channel. data is valid on the rising edge of serial clock. the msb is left-justified to an lrclk transition but with a single serial clock period delay. figure 33 shows the left-justified mo de. lrclk is high for the left channel and lo for the right channel. data is valid on the rising edge of serial clock. th e msb is left-justified to an lrclk transition with no msb delay. figure 31. right-justified mode figure 32. i 2 s-justified mode figure 33. left-justified mode mb ha hha b b mb mb mb mb mb b+ b+ b b+ b+ a a a aa ha hha b mb mb b+ b+ mbm b b mb mb b+ b+ a a a aa mb ha hha mb b mb mb mb mb mb mb+ mb b+ b+ b b+ b+ a a a aa
rev. pre | page 48 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data s/pdif transmitter input data timing the timing requirements for th e s/pdif transmitter are given in table 41 . input signals are routed to the dai_p20C1 pins using the sru. therefore, the ti ming specifications provided below are valid at the dai_p20C1 pins. oversampling clock (hfclk) switching characteristics the s/pdif transmitter has an oversampling clock. this hfclk input is divided down to generate the biphase clock. table 41. s/pdif transmitter input data timing parameter min max unit timing requirements t sisfs 1 frame sync setup before serial clock rising edge 3 ns t sihfs 1 frame sync hold after serial clock rising edge 3 ns t sisd 1 data setup before serial clock rising edge 3 ns t sihd 1 data hold after serial clock rising edge 3 ns t sihfclkw transmit clock width 36 ns t sihfclk transmit clock period 80 ns t sisclkw clock width 9 ns t sisclk clock period 20 ns 1 the serial clock, data and frame sync signals can come from any of the dai pins.the serial clock and frame sync signals can als o come via pcg or sports. pcgs input can be either clkin or any of the dai pins. figure 34. s/pdif transmitter input timing sple edge di_p20C1 (txclk) di_p20C1 (seril clock) di_p20C1 (fre sync) di_p20C1 (dt) t sitxclkw t sitxclk t sisclkw t sisclk t sisfs t sifs t sisd t sid table 42. over sampling clock (h fclk) switching characteristics parameter max unit hfclk frequency for hfclk = 384 frame sync oversampling ratio frame sync <= 1/t sihfclk mhz hfclk frequency for hfclk = 256 frame sync 49.2 mhz frame rate (fs) 192.0 khz
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 49 of 68 | november 2009 s/pdif receiver the following section describes timing as it relates to the s/pdif receiver. internal digital pll mode in the internal digital phase-lock ed loop mode the internal pll (digital pll) generates the tbd fs clock. table 43. s/pdif receiver inte rnal digital pll mode timing parameter min max unit switching characteristics t dfsi lrclk delay after serial clock 5 ns t hofsi lrclk hold after serial clock C2 ns t ddti transmit data delay after serial clock 5 ns t hdti transmit data hold after serial clock C2 ns t sclkiw 1 transmit serial clock width 40 ns 1 serial clock frequency is tbd x frame sync where fs = the frequency of lrclk. figure 35. s/pdif receiver internal digital pll mode timing da (a) am a (amy) a (aaha a/b) w h h
rev. pre | page 50 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data spi interfacemaster the adsp-2146x contains two spi ports. both pr imary and sec- ondary are available through dpi only. the timing provided in table 44 and table 45 applies to both. table 44. spi interface protocolmaster switching and timing specifications parameter min max unit timing requirements t sspidm data input valid to spiclk edge (data input setup time) 8.2 ns t hspidm spiclk last sampling edge to data input not valid 2 ns switching characteristics t spiclkm serial clock cycle 8 t pclk C 2 ns t spichm serial clock high period 4 t pclk C 2 ns t spiclm serial clock low period 4 t pclk C 2 ns t ddspidm spiclk edge to data out valid (data out delay time) 2.5 ns t hdspidm spiclk edge to data out not valid (data out hold time) 4 t pclk C 2 ns t sdscim dpi pin (spi device select) low to first spiclk edge 4 t pclk C 2 ns t hdsm last spiclk edge to dpi pin (spi device select) high 4 t pclk C 2 ns t spitdm sequential transfer delay 4 t pclk C 1 ns figure 36. spi master timing t spichm m m m hm m m hm mb a ba mba b b mb mb m hm m ba in () (=) () (=) () m () m () m () m () ha= ha= hm hm hm m m m hm
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 51 of 68 | november 2009 spi interfaceslave table 45. spi interface protocolslave switching and timing specifications parameter min max unit timing requirements t spiclks serial clock cycle 4 t pclk C 2 ns t spichs serial clock high period 2 t pclk C 2 ns t spicls serial clock low period 2 t pclk C 2 ns t sdsco spids assertion to first spiclk edge, cphase = 0 or cphase = 1 2 t pclk ns t hds last spiclk edge to spids not asserted, cphase = 0 2 t pclk ns t sspids data input valid to spiclk edge (data input setup time) 2 ns t hspids spiclk last sampling edge to data input not valid 2 ns t sdppw spids deassertion pulse width (cphase = 0) 2 t pclk ns switching characteristics t dsoe spids assertion to data out active 0 6.8 ns t dsoe 1 spids assertion to data out active (spi2) 0 8 ns t dsdhi spids deassertion to data high impedance 0 6.8 ns t dsdhi 1 spids deassertion to data high impedance (spi2) 0 8.6 ns t ddspids spiclk edge to data out valid (data out delay time) 9.5 ns t hdspids spiclk edge to data out not valid (data out hold time) 2 t pclk ns t dsov spids assertion to data out valid (cphase = 0) 5 t pclk ns 1 the timing for these parameters applies when the spi is routed through the signal routing unit. for more information, see the p rocessor hardware refere nce, serial peripheral interface port chapter.
rev. pre | page 52 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data figure 37. spi slave timing t spichs t spicls t spiclks t hds t sdppw t sdsco t spicls t spichs t dsoe t ddspids t ddspids t dsdhi t hdspids t hspids t sspids msb valid lsb valid msb valid t sspids lsb lsb msb msb t dsdhi t ddspids t dsov t hspids t sspids t hdspids lsb valid spids (input) spiclk (cp = 0) (input) spiclk (cp = 1) (input) miso (output) mosi (input) miso (output) mosi (input) cphase = 1 cphase = 0
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 53 of 68 | november 2009 media local bus all the numbers given are appl icable for all speed modes (1024fs, 512fs and 256fs for 3-pin; 512fs and 256fs for 5-pin) unless otherwise specified. please refer to medialb specification document rev 3.0 for more details. table 46. mlb interface, 3-pin specifications parameter min typ max unit three-pin characteristics t mlbclk mlb clock period 1024fs 512fs 256fs 20.3 40 81 ns ns ns t mckl mlbclk low time 1024fs 512fs 256fs 6.1 14 30 ns ns ns t mckh mlbclk high time 1024fs 512fs 256fs 9.3 14 30 ns ns ns t mckr mlbclk rise time (v il to v ih ) 1024fs 512fs/256fs 1 3 ns ns t mckf mlbclk fall time (v ih to v il ) 1024fs 512fs/256fs 1 3 ns ns t mpwv 1 mlbclk pulse width variation 1024fs 512fs/256 0.7 2.0 nspp nspp t dsmcf dat/sig input setup time 1 ns t dhmcf dat/sig input hold time 0 ns t mcfdz dat/sig output time to three-state 0 t mckl ns t mcdrv dat/sig output data delay from mlbclk rising edge 8 ns t mdzh 2 bus hold time 1024fs 512fs/256 2 4 ns ns c mlb dat/sig pin load 1024fs 512fs/256 40 60 pf pf 1 pulse width variation is measured at 1.25 v by triggering on one edge of mlbclk and measuring the spread on the other edge, mea sured in ns pe ak-to-peak(pp). 2 the board must be designed to insure that the high-impedance bus does no t leave the logic state of th e final driven bit for thi s time period. therefore, coupling must be minimized while meeting the ma ximum capacitive load listed.
rev. pre | page 54 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data figure 38. mlb timing (3-pin interface) table 47. mlb interface, 5-pin specifications parameter min typ max unit five-pin characteristics t mlbclk mlb clock period 512fs 256fs 40 81 ns ns t mckl mlbclk low time 512fs 256fs 15 30 ns ns t mckh mlbclk high time 512fs 256fs 15 30 ns ns t mckr mlbclk rise time (v il to v ih )6 n s t mckf mlbclk fall time (v ih to v il )6 n s t mpwv 1 mlbclk pulse width variation 2 nspp t dsmcf 2 dat/sig input setup time 3 ns t dhmcf dat/sig input hold time 5 ns t mcdrv ds/do output data delay from mlbclk rising edge 8 ns t mcrdl 3 do/so low from mlbclk high 512fs 256fs 10 20 ns ns c mlb ds/do pin load 40 pf 1 pulse width variation is measured at 1.25 v by triggering on one edge of mlbclk and measuring the spread on the other edge, mea sured in ns peak -to-peak (pp). 2 gate delays due to or'ing logic on the pins must be accounted for. 3 when a node is not driving valid data onto the bus, the mlbso and mlbdo output lines shall remain low. if the output lines can float at anytime, incl uding while in reset, external pull-down resistors are required to keep the outputs fr om corrupting the medialb signal lines when not being driven. t ck lsig/ mldt rx, iput) t mckl t mckr mlbsig/ mlbdat (tx, output) t mcfdz t dsmcf mlbclk t mlbclk valid t dhmcf t mckf t mcdrv valid t mdzh
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 55 of 68 | november 2009 figure 39. mlb timing (5-pin interface) figure 40. mlb 3-pin and 5-pin ml bclk pulse width variation timing t mckh mlbsig/ mlbdat (rx, input) t mckl t mckr mlbso/ mlbdo (tx, output) t mcrdl t dsmcf mlbclk t mlbclk valid valid t dhmcf t mckf t mcdrv t mpwv t mpwv mlbclk
rev. pre | page 56 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data universal asynchronous receiver-transmitter (uart) portreceive and transmit timing figure 41 describes uart port receiv e and transmit operations. the maximum baud rate is pclk/16 where pclk = 1/tpclk. as shown in figure 41 there is some latency between the gener- ation of internal uart interrupts and the external data operations. these latencies are ne gligible at the data transmis- sion rates for the uart. table 48. uart port parameter min max unit timing requirement t rxd 1 incoming data pulse width 16 t pclk C1 ns switching characteristic t txd 1 outgoing data pulse width 16 t pclk C1 ns 1 uart signals rxd and txd are routed through dpi p14-1 pins using the sru. figure 41. uart portreceive and transmit timing dpi_p14 [x] 4 [x] aa(58) aa(58) a a a aam abbyaa; abya aambbyam; abywam a () am
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 57 of 68 | november 2009 twi controller timing table 49 and figure 42 provide timing information for the twi interface. input signals (scl , sda) are routed to the dpi_p14C1 pins using the sru. therefore, the timing specifica- tions provided below are va lid at the dpi_p14C1 pins. table 49. characteristics of the sda and scl bus lines for f/s-mode twi bus devices 1 parameter standard mode fast mode min max min max unit f scl scl clock frequency 0 100 0 400 khz t hdsta hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 0.6 s t low low period of the scl clock 4.7 1.3 s t high high period of the scl clock 4.0 0.6 s t susta setup time for a repeated start condition 4.7 0.6 s t hddat data hold time for twi-bus devices 0 0 s t sudat data setup time 250 100 ns t susto setup time for stop condition 4.0 0.6 s t buf bus free time between a stop and start condition 4.7 1.3 s t sp pulse width of spikes suppressed by the input filter n/a n/a 0 50 ns 1 all values referred to v ihmin and v ilmax levels. for more information, see electr ical characteristics on page 20. figure 42. fast and standard mode timing on the twi bus ps s sr 4 a 4 b a hh ha ha ha a w
rev. pre | page 58 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data jtag test access port and emulation table 50. jtag test access port and emulation parameter min max unit timing requirements t tck tck period t ck ns t stap tdi, tms setup before tck high 5 ns t htap tdi, tms hold after tck high 6 ns t ssys 1 system inputs setup before tck high 7 ns t hsys 1 system inputs hold after tck high 18 ns t trstw trst pulse width 4 t ck ns switching characteristics t dtdo tdo delay from tck low 7 ns t dsys 2 system outputs delay after tck low t ck 2 + 7 ns 1 system inputs = ami_data, ddr2_data, clkcfg1 -0, bootcfg2-0 reset, dai, dpi, flag3-0. 2 system outputs = ami_addr/data, ddr2_addr/data, ami_ctrl, ddr2_ctrl, dai, dpi, flag3-0, emu . figure 43. ieee 1149.1 jtag test access port tck tm ym ym a ha y hy y
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 59 of 68 | november 2009 output drive currents figure 44 shows typical i-v characteri stics for the output driv- ers of the adsp-2146x. the curves represent the current drive capability of the output drivers as a function of output voltage. test conditions the ac signal specifications (timing parameters) appear in table 17 on page 26 through table 50 on page 58 . these include output disable time, output enable time, and capacitive loading. the timing specifications for the sharc apply for the voltage reference levels in figure 45 . timing is measured on signals wh en they cross the 1.5 v level as described in figure 46 . all delays (in nanoseconds) are mea- sured between the point that the first signal reaches 1.5 v and the point that the second signal reaches 1.5 v. capacitive loading output delays and holds are based on standard capacitive loads: 30 pf on all pins (see figure 45 ). figure 49 shows graphically how output delays and holds vary with load capacitance. the graphs of figure 47 , figure 48 , and figure 49 may not be linear outside the ranges shown for typical output delay vs. load capacitance and typical output rise time (20% to 80%, v = min) vs. load capacitance. figure 44. typical drive at junction temperature figure 45. equivalent device loading for ac measurements (includes all fixtures) 8 0 0 100 250 12 4 2 10 6 200 150 50 tbd t1 zo = 50:(impedance) td = 4.04 r 1.18 ns 2pf tester pin electronics 50 : 0.5pf 70 : 400 : 45 : 4pf notes: the worst case transmission line delay is shown and can be used for the output timing analysis to refelect the transmission line effect and must be considered. the transmission line (td), is for load only and does not affect the data sheet timing specifications. analog devices recommends using the ibis model timing for a given system requirement. if necessary, a system may incorporate external drivers to compensate for any timing differences. v load dut output 50 : figure 46. voltage reference levels for ac measurements figure 47. typical output rise/fall time (20% to 80%, v dd_ext = max) figure 48. typical output rise/fall time (20% to 80%, v dd_ext = min) input or output 1.5v 1.5v load capacitance (pf) 8 0 0 100 250 12 4 2 10 6 ri s e an d fa l l t i me s (n s ) 200 150 50 fall y = 0.0467x + 1.6323 y=0.045x+1.524 rise load capacitance (pf) 12 0 50 100 150 200 250 10 8 6 4 r is e a n d fa l l t im es ( n s) 2 0 rise fall y = 0.049x + 1.5105 y = 0.0482x + 1.4604
rev. pre | page 60 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data thermal characteristics the adsp-2146x processor is ra ted for performance over the temperature range specified in operating conditions on page 19 . table 51 airflow measurements comp ly with jedec standards jesd51-2 and jesd51-6 and the junction-to-board measure- ment complies with jesd51-8. te st board design complies with jedec standards jesd51-7 (csp_b ga). the junction-to-case measurement complies with mi l- std-883. all measurements use a 2s2p jedec test board. to determine the junction temperature of the device while on the application pcb, use: where: t j = junction temperature c t case = case temperature ( c) measured at the top center of the package jt = junction-to-top (of package) characterization parameter is the typical value from table 51 . p d = power dissipation values of ja are provided for package comparison and pcb design considerations. ja can be used for a first order approxi- mation of t j by the equation: where: t a = ambient temperature c values of jc are provided for pack age comparison and pcb design considerations when an external heatsink is required. values of jb are provided for pack age comparison and pcb design considerations. note that the thermal characteristics val- ues provided in table 51 are modeled values. figure 49. typical output delay or hold vs. load capacitance (at ambient temperature) load capacitance (pf) 02 0 0 50 100 150 10 8 o u t p u t d e l a or h o l d (n s) - 4 6 0 4 2 - 2 y=0.0488x - 1.5923 t j t case jt p d () += t j t a ja p d () += table 51. thermal characteristics for 324-lead csp_bga parameter condition typical unit ja airflow = 0 m/s tbd c/w jma airflow = 1 m/s tbd c/w jma airflow = 2 m/s tbd c/w jc tbd c/w jt airflow = 0 m/s tbd c/w jmt airflow = 1 m/s tbd c/w jmt airflow = 2 m/s tbd c/w
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 61 of 68 | november 2009 csp_bga ball assignment C adsp -21462w/adsp-21465w/adsp-21469w table 52 lists the csp_bga ball names. for default dai and dpi routing, see the processo r hardware reference manual. table 52. csp_bga ball assignment (alphabetically by signal) signal ball no. signal ball signal ball signal ball agnd h02 clk_cfg1 g02 ddr2_cke e01 dpi_p09 n01 ami_ack r10 clkin l01 ddr2_clk0 a07 dpi_p10 n02 ami_addr0 v16 dai_p01 r06 ddr2_clk0 b07 dpi_p11 n03 ami_addr01 u16 dai_p02 v05 ddr2_clk1 a13 dpi_p12 n04 ami_addr02 t16 dai_p03 r07 ddr2_clk1 b13 dpi_p13 m03 ami_addr03 r16 dai_p04 r03 ddr2_cs0 c01 dpi_p14 m04 ami_addr04 v15 dai_p05 u05 ddr2_cs1 d01 emu k02 ami_addr05 u15 dai_p06 t05 ddr2_cs2 c02 flag0 r08 ami_addr06 t15 dai_p07 v06 ddr2_cs3 d02 flag1 v07 ami_addr07 r15 dai_p08 v02 ddr2_data0 b02 flag2 u07 ami_addr08 v14 dai_p09 r05 ddr2_data01 a02 flag3 t07 ami_addr09 u14 dai_p10 v04 ddr2_data02 b03 gnd a01 ami_addr10 t14 dai_p11 u04 ddr2_data03 a03 gnd a18 ami_addr11 r14 dai_p12 t04 ddr2_data04 b05 gnd c04 ami_addr12 v13 dai_p13 u06 ddr2_data05 a05 gnd c06 ami_addr13 u13 dai_p14 u02 ddr2_data06 b06 gnd c08 ami_addr14 t13 dai_p15 r04 ddr2_data07 a06 gnd d05 ami_addr15 r13 dai_p16 v03 ddr2_data08 b08 gnd d07 ami_addr16 v12 dai_p17 u03 ddr2_data09 a08 gnd d09 ami_addr17 u12 dai_p18 t03 ddr2_data10 b09 gnd d10 ami_addr18 t12 dai_p19 t06 ddr2_data11 a09 gnd d17 ami_addr19 r12 dai_p20 t02 ddr2_data12 a11 gnd e03 ami_addr20 v11 ddr2_addr0 d13 ddr2_data13 b11 gnd e05 ami_addr21 u11 ddr2_addr01 c13 ddr2_data14 a12 gnd e12 ami_addr22 t11 ddr2_addr02 d14 ddr2_data15 b12 gnd e13 ami_addr23 r11 ddr2_addr03 c14 ddr2_dm0 c03 gnd e16 ami_data0 u18 ddr2_addr04 b14 ddr2_dm1 c11 gnd f01 ami_data1 t18 ddr2_addr05 a14 ddr2_dqs0 a04 gnd f02 ami_data2 r18 ddr2_addr06 d15 ddr2_dqs0 b04 gnd f04 ami_data3 p18 ddr2_addr07 c15 ddr2_dqs1 a10 gnd f14 ami_data4 v17 ddr2_addr08 b15 ddr2_dqs1 b10 gnd f16 ami_data5 u17 ddr2_addr09 a15 ddr2_odt b01 gnd g03 ami_data6 t17 ddr2_addr10 d16 ddr2_ras c09 gnd g04 ami_data7 r17 ddr2_addr11 c16 ddr2_we c10 gnd g05 ami_ms0 t10 ddr2_addr12 b16 dpi_p01 r02 gnd g07 ami_ms1 u10 ddr2_addr13 a16 dpi_p02 u01 gnd g08 ami_rd j04 ddr2_addr14 b17 dpi_p03 t01 gnd g09 ami_wr v10 ddr2_addr15 a17 dpi_p04 r01 gnd g10 boot_cfg0 j02 ddr2_ba0 c18 dpi_p05 p01 gnd g11 boot_cfg1 j03 ddr2_ba1 c17 dpi_p06 p02 gnd g12 boot_cfg2 ho3 ddr2_ba2 b18 dpi_p07 p03 gnd g15 clk_cfg0 g01 ddr2_cas c07 dpi_p08 p04 gnd h04
rev. pre | page 62 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data gnd h07 gnd v01 v dd _ ddr 2 e04 v dd _ int f12 gnd h08 gnd v18 v dd _ ddr 2 e07 v dd _ int f13 gnd h09 lack_0 k17 v dd _ ddr 2 e10 v dd _ int g06 gnd h10 lack_1 p17 v dd _ ddr 2 e11 v dd _ int g13 gnd h11 lclk_0 j18 v dd _ ddr 2 e17 v dd _ int h05 gnd h12 lclk_1 n18 v dd _ ddr 2 f03 v dd _ int h06 gnd j01 ldat0_0 e18 v dd _ ddr 2 f05 v dd _ int h13 gnd j07 ldat0_1 f17 v dd _ ddr 2 f15 v dd _ int h14 gnd j08 ldat0_2 f18 v dd _ ddr 2 g14 v dd _ int j06 gnd j09 ldat0_3 g17 v dd _ ddr 2 g16 v dd _ int j13 gnd j10 ldat0_4 g18 v dd _ ext h15 v dd _ int k06 gnd j11 ldat0_5 h16 v dd _ ext h18 v dd _ int k13 gnd j12 ldat0_6 h17 v dd _ ext j05 v dd _ int l06 gnd j14 ldat0_7 j16 v dd _ ext j15 v dd _ int l13 gnd j17 ldat1_0 k18 v dd _ ext k14 v dd _ int m06 gnd k05 ldat1_1 l16 v dd _ ext l05 v dd _ int m13 gnd k07 ldat1_2 l17 v dd _ ext m14 v dd _ int n06 gnd k08 ldat1_3 l18 v dd _ ext m18 v dd _ int n07 gnd k09 ldat1_4 m16 v dd _ ext n05 v dd _ int n08 gnd k10 ldat1_5 m17 v dd _ ext n10 v dd _ int n09 gnd k11 ldat1_6 n16 v dd _ ext p06 v dd _ int n13 gnd k12 ldat1_7 p16 v dd _ ext p08 v ref d04 gnd l07 mlbclk k03 v dd _ ext p10 v ref d11 gnd l08 mlbdat k04 v dd _ ext p12 xtal k01 gnd l09 mlbdo l02 v dd _ ext p14 gnd l10 mlbsig l03 v dd _ ext p15 gnd l11 mlbso l04 v dd _ ext t08 gnd l12 reset m01 v dd _ ext t09 gnd l14 resetout /runrstin m02 v dd _ ext u08 gnd m05 tck k15 v dd _ ext u09 gnd m07 tdi l15 v dd _ ext v08 gnd m08 tdo m15 v dd _ ext v09 gnd m09 thd_m n12 v dd _ int d12 gnd m10 thd_p n11 v dd _ int e06 gnd m11 tms k16 v dd _ int e08 gnd m12 trst n15 v dd _ int e09 gnd n14 vdd_a h01 v dd _ int e14 gnd n17 v dd _ ddr 2 c05 v dd _ int e15 gnd p05 v dd _ ddr 2 c12 v dd _ int f06 gnd p07 v dd _ ddr 2 d03 v dd _ int f07 gnd p09 v dd _ ddr 2 d06 v dd _ int f08 gnd p11 v dd _ ddr 2 d08 v dd _ int f09 gnd p13 v dd _ ddr 2 d18 v dd _ int f10 gnd r09 v dd _ ddr 2 e02 v dd _ int f11 table 52. csp_bga ball assignment (alp habetically by signal) (continued) signal ball no. signal ball signal ball signal ball
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 63 of 68 | november 2009 figure 50. adsp-21462w/adsp-21465w/adsp-21469w ball configuration C pin out 4 2 5 3 1 6789 10 11 12 1 3 14 15 17 16 18 a1 corner index area a b c d e f g h j k l m n p r t u v d r r r t t a s a s v dd_thd v ref v dd_ddr2 v dd_int v dd_ext gnd agnd v dd_a d d d d d d d d d d d d d d d d d i/o signals
rev. pre | page 64 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data csp_bga ball assignment - adsp-21467/adsp-21469 table 53 lists the ball names. table 53. csp_bga ball assignment (alphabetically by signal) signal ball no. signal ball signal ball signal ball agnd h02 clk_cfg1 g02 ddr2_cke e01 dpi_p09 n01 ami_ack r10 clkin l01 ddr2_clk0 a07 dpi_p10 n02 ami_addr0 v16 dai_p01 r06 ddr2_clk0 b07 dpi_p11 n03 ami_addr01 u16 dai_p02 v05 ddr2_clk1 a13 dpi_p12 n04 ami_addr02 t16 dai_p03 r07 ddr2_clk1 b13 dpi_p13 m03 ami_addr03 r16 dai_p04 r03 ddr2_cs0 c01 dpi_p14 m04 ami_addr04 v15 dai_p05 u05 ddr2_cs1 d01 emu k02 ami_addr05 u15 dai_p06 t05 ddr2_cs2 c02 flag0 r08 ami_addr06 t15 dai_p07 v06 ddr2_cs3 d02 flag1 v07 ami_addr07 r15 dai_p08 v02 ddr2_data0 b02 flag2 u07 ami_addr08 v14 dai_p09 r05 ddr2_data01 a02 flag3 t07 ami_addr09 u14 dai_p10 v04 ddr2_data02 b03 gnd a01 ami_addr10 t14 dai_p11 u04 ddr2_data03 a03 gnd a18 ami_addr11 r14 dai_p12 t04 ddr2_data04 b05 gnd c04 ami_addr12 v13 dai_p13 u06 ddr2_data05 a05 gnd c06 ami_addr13 u13 dai_p14 u02 ddr2_data06 b06 gnd c08 ami_addr14 t13 dai_p15 r04 ddr2_data07 a06 gnd d05 ami_addr15 r13 dai_p16 v03 ddr2_data08 b08 gnd d07 ami_addr16 v12 dai_p17 u03 ddr2_data09 a08 gnd d09 ami_addr17 u12 dai_p18 t03 ddr2_data10 b09 gnd d10 ami_addr18 t12 dai_p19 t06 ddr2_data11 a09 gnd d17 ami_addr19 r12 dai_p20 t02 ddr2_data12 a11 gnd e03 ami_addr20 v11 ddr2_addr0 d13 ddr2_data13 b11 gnd e05 ami_addr21 u11 ddr2_addr01 c13 ddr2_data14 a12 gnd e12 ami_addr22 t11 ddr2_addr02 d14 ddr2_data15 b12 gnd e13 ami_addr23 r11 ddr2_addr03 c14 ddr2_dm0 c03 gnd e16 ami_data0 u18 ddr2_addr04 b14 ddr2_dm1 c11 gnd f01 ami_data1 t18 ddr2_addr05 a14 ddr2_dqs0 a04 gnd f02 ami_data2 r18 ddr2_addr06 d15 ddr2_dqs0 b04 gnd f04 ami_data3 p18 ddr2_addr07 c15 ddr2_dqs1 a10 gnd f14 ami_data4 v17 ddr2_addr08 b15 ddr2_dqs1 b10 gnd f16 ami_data5 u17 ddr2_addr09 a15 ddr2_odt b01 gnd g03 ami_data6 t17 ddr2_addr10 d16 ddr2_ras c09 gnd g04 ami_data7 r17 ddr2_addr11 c16 ddr2_we c10 gnd g05 ami_ms0 t10 ddr2_addr12 b16 dpi_p01 r02 gnd g07 ami_ms1 u10 ddr2_addr13 a16 dpi_p02 u01 gnd g08 ami_rd j04 ddr2_addr14 b17 dpi_p03 t01 gnd g09 ami_wr v10 ddr2_addr15 a17 dpi_p04 r01 gnd g10 boot_cfg0 j02 ddr2_ba0 c18 dpi_p05 p01 gnd g11 boot_cfg1 j03 ddr2_ba1 c17 dpi_p06 p02 gnd g12 boot_cfg2 ho3 ddr2_ba2 b18 dpi_p07 p03 gnd g15 clk_cfg0 g01 ddr2_cas c07 dpi_p08 p04 gnd h04
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 65 of 68 | november 2009 gnd h07 gnd v01 v dd _ ddr 2 e04 v dd _ int f12 gnd h08 gnd v18 v dd _ ddr 2 e07 v dd _ int f13 gnd h09 lack_0 k17 v dd _ ddr 2 e10 v dd _ int g06 gnd h10 lack_1 p17 v dd _ ddr 2 e11 v dd _ int g13 gnd h11 lclk_0 j18 v dd _ ddr 2 e17 v dd _ int h05 gnd h12 lclk_1 n18 v dd _ ddr 2 f03 v dd _ int h06 gnd j01 ldat0_0 e18 v dd _ ddr 2 f05 v dd _ int h13 gnd j07 ldat0_1 f17 v dd _ ddr 2 f15 v dd _ int h14 gnd j08 ldat0_2 f18 v dd _ ddr 2 g14 v dd _ int j06 gnd j09 ldat0_3 g17 v dd _ ddr 2 g16 v dd _ int j13 gnd j10 ldat0_4 g18 v dd _ ext h15 v dd _ int k06 gnd j11 ldat0_5 h16 v dd _ ext h18 v dd _ int k13 gnd j12 ldat0_6 h17 v dd _ ext j05 v dd _ int l06 gnd j14 ldat0_7 j16 v dd _ ext j15 v dd _ int l13 gnd j17 ldat1_0 k18 v dd _ ext k14 v dd _ int m06 gnd k05 ldat1_1 l16 v dd _ ext l05 v dd _ int m13 gnd k07 ldat1_2 l17 v dd _ ext m14 v dd _ int n06 gnd k08 ldat1_3 l18 v dd _ ext m18 v dd _ int n07 gnd k09 ldat1_4 m16 v dd _ ext n05 v dd _ int n08 gnd k10 ldat1_5 m17 v dd _ ext n10 v dd _ int n09 gnd k11 ldat1_6 n16 v dd _ ext p06 v dd _ int n13 gnd k12 ldat1_7 p16 v dd _ ext p08 v ref d04 gnd l07 nc k03 v dd _ ext p10 v ref d11 gnd l08 nc k04 v dd _ ext p12 xtal k01 gnd l09 nc l02 v dd _ ext p14 gnd l10 nc l03 v dd _ ext p15 gnd l11 nc l04 v dd _ ext t08 gnd l12 reset m01 v dd _ ext t09 gnd l14 resetout /runrstin m02 v dd _ ext u08 gnd m05 tck k15 v dd _ ext u09 gnd m07 tdi l15 v dd _ ext v08 gnd m08 tdo m15 v dd _ ext v09 gnd m09 thd_m n12 v dd _ int d12 gnd m10 thd_p n11 v dd _ int e06 gnd m11 tms k16 v dd _ int e08 gnd m12 trst n15 v dd _ int e09 gnd n14 vdd_a h01 v dd _ int e14 gnd n17 v dd _ ddr 2 c05 v dd _ int e15 gnd p05 v dd _ ddr 2 c12 v dd _ int f06 gnd p07 v dd _ ddr 2 d03 v dd _ int f07 gnd p09 v dd _ ddr 2 d06 v dd _ int f08 gnd p11 v dd _ ddr 2 d08 v dd _ int f09 gnd p13 v dd _ ddr 2 d18 v dd _ int f10 gnd r09 v dd _ ddr 2 e02 v dd _ int f11 table 53. csp_bga ball assignment (alp habetically by signal) (continued) signal ball no. signal ball signal ball signal ball
rev. pre | page 66 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data figure 51. adsp-21467/adsp-21469 ball configuration - pin out 4 2 53 1 6789 10 11 12 1 3 14 15 17 16 18 a1 corner index area a b c d e f g h j k l m n p r t u v d r r r nc t t a s a s v dd_thd v ref v dd_ddr2 v dd_int v dd_ext gnd agnd v dd_a d d d d d d d d d d d d d d d d d i/o signals
adsp-21462w/adsp-21465w/adsp -21467/adsp-21469/adsp-21469w preliminary technical data rev. pre | page 67 of 68 | november 2009 outline dimensions the adsp-2146x processors are av ailable in a 19 mm by 19 mm csp_bga lead-free package. surface-mount design the following table is provided as an aid to pcb design. for industry-standard desi gn recommendations, refer to ipc-7351, generic requirements for surfac e mount design and land pat- tern standard . figure 52. 324-ball plastic ball grid array [csp_bga] (bc-324-1) dimensions shown in millimeters * compliant to jedec standards mo-192-aag-1 with the exception to package height. 1.00 bsc 1.00 ref a b c d e f g 9 8 11 10 1 3 12 7 6 5 4 2 3 1 bottom view 17.00 bsc sq h j k l m n p r t u v 0.50 nom 0.45 min detail a top view detail a coplanarity 0.20 0.70 0.60 0.50 ball diameter seating plane 19.10 19.00 sq 18.90 a1 ball corner a1 ball corner * 1.80 1.71 1.56 1.31 1.21 1.11 1 5 1 4 1 7 1 6 1 8 package package ball attach type package metal pad package solder mask opening package ball pad size 324-ball csp_bga (bc-324-1) solder mask defined 0.60 mm on laminate 0.43 mm diameter 0.6 mm diameter
rev. pre | page 68 of 68 | november 2009 adsp-21462w/adsp-21465w/adsp- 21467/adsp-21469/adsp-21469w preliminary technical data ? 2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. pr07900 - 0-11/09(pre) automotive products the adsp-21462w, adsp-21465w, and adsp -21469w are available for automotive applicat ions with controlled manufacturing. note that these special models may have specificatio ns that differ from the general release models. the automotive grade products shown in table 54 are available for use in automotive applications. contact your local adi account repre- sentative or authorized adi product distribu tor for specific product ordering informatio n. note that all automotive products ar e rohs compliant. ordering guide table 54. automotive products model 1 1 z =rohs compliant part temperature range 2 2 referenced temperature is ambient temperature. on-chip sram rom package description package option ad21462wbcz3xx C40c to +85c 5m bit n/a 324-ball grid array (csp_bga) bc-324-1 ad21465wbcz3xx C40c to +85c 5m bit 4m bit 324-ball grid array (csp_bga) bc-324-1 ad21469wbcz3xx C40c to +85c 5m bit n/a 324-ball grid array (csp_bga) bc-324-1 model 1 1 z =rohs compliant part. temperature range 2 2 referenced temperature is ambient temperature. on-chip sram rom package description package option ADSP-21462BBCZ-ENG C40 c to +85 c 5 mbit 4 mbit 324-ball grid array (csp_bga) bc-324-1 adsp-21467kbcz-eng 3 3 available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. fo r a complete list, visit our website at www.analog.com/sharc. 0 c to +70 c 5 mbit 4 mbit 324-ball grid array (csp_bga) bc-324-1 adsp-21469kbcz-eng 0 c to +70 c 5 mbit n/a 324-ball grid array (csp_bga) bc-324-1

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